`timescale 10ns/1ns
module orDoor (
    input a,
    input b,
    output c
);

assign c = a || b;
    
endmodule

module test;
    reg a , b;
    wire c;
    orDoor nnt(
        .a(a),
        .b(b),
        .c(c)
    );

    initial begin
    $dumpfile("ez.vcd");
    $dumpvars(0 , test);

    #10 a = 0;b = 0;
    #10 $display("%d %d %d", a , b , c);

    #10 a = 0;b = 1;
    #10 $display("%d %d %d", a , b , c);
#10
    a = 1;b = 0;
    #10 $display("%d %d %d", a , b , c);
#10
    a = 1;b = 1;
    #10 $display("%d %d %d", a , b , c);
    end

endmodule