module pwm_tb;
    reg clk = 0;
    reg rst = 0;
    reg [7:0] duty = 128;  // 默认占空比50%
    wire pwm_out;

    
    // 实例化
    pwm uut (
        .clk(clk),
        .rst(rst),
        .duty(duty),
        .pwm_out(pwm_out)
    );

    // 模拟时钟，每 10ns 反转一次，相当于 50MHz
    always #10 clk = ~clk;

    initial begin
        // 复位一段时间
        $dumpfile("wave.vcd");
        $dumpvars(0, pwm_tb);
        rst = 1;
        #20;
        rst = 0;

        // 运行一段时间后改变占空比
        #1000;
        duty = 64;   // 25%
        #1000;
        duty = 192;  // 75%
        #1000;
        $finish;
    end

endmodule