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e2hang aca5a8aab8 New Hardware Git
2025-12-31 19:35:06 +08:00
CPU
New Hardware Git
2025-12-31 19:35:06 +08:00
Logisim
New Hardware Git
2025-12-31 19:35:06 +08:00
Verilog
New Hardware Git
2025-12-31 19:35:06 +08:00
readme.md
New Hardware Git
2025-12-31 19:35:06 +08:00

readme.md

硬件实验

采用Logisim 3.9 以及 Verilog制作

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Description
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Readme 27 MiB
Languages
Assembly 63.5%
Verilog 36.5%