84 lines
2.9 KiB
XML
84 lines
2.9 KiB
XML
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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<project source="2.7.1" version="1.0">
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This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).
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<lib desc="#Wiring" name="0"/>
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<lib desc="#Gates" name="1"/>
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<lib desc="#Plexers" name="2"/>
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<lib desc="#Arithmetic" name="3"/>
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<lib desc="#Memory" name="4"/>
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<lib desc="#I/O" name="5"/>
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<lib desc="#Base" name="6">
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<tool name="Text Tool">
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<a name="text" val=""/>
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<a name="font" val="SansSerif plain 12"/>
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<a name="halign" val="center"/>
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<a name="valign" val="base"/>
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</tool>
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</lib>
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<main name="INV_OC"/>
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<options>
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<a name="gateUndefined" val="ignore"/>
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<a name="simlimit" val="1000"/>
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<a name="simrand" val="0"/>
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</options>
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<mappings>
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<tool lib="6" map="Button2" name="Menu Tool"/>
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<tool lib="6" map="Button3" name="Menu Tool"/>
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<tool lib="6" map="Ctrl Button1" name="Menu Tool"/>
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</mappings>
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<toolbar>
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<tool lib="6" name="Poke Tool"/>
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<tool lib="6" name="Edit Tool"/>
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<tool lib="6" name="Text Tool">
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<a name="text" val=""/>
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<a name="font" val="SansSerif plain 12"/>
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<a name="halign" val="center"/>
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<a name="valign" val="base"/>
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</tool>
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<sep/>
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<tool lib="0" name="Pin">
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<a name="tristate" val="false"/>
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</tool>
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<tool lib="0" name="Pin">
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<a name="facing" val="west"/>
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<a name="output" val="true"/>
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<a name="labelloc" val="east"/>
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</tool>
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<tool lib="1" name="NOT Gate">
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<a name="size" val="20"/>
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</tool>
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<tool lib="1" name="AND Gate"/>
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<tool lib="1" name="OR Gate"/>
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</toolbar>
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<circuit name="INV_OC">
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<a name="circuit" val="INV_OC"/>
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<a name="clabel" val=""/>
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<a name="clabelup" val="east"/>
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<a name="clabelfont" val="SansSerif plain 12"/>
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<appear>
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<polyline fill="#ffffff" points="60,40 120,70 60,100 60,41" stroke="#000000" stroke-width="2"/>
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<ellipse cx="125.0" cy="70.0" fill="#ffffff" rx="5.0" ry="5.0" stroke="#000000" stroke-width="2"/>
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<polyline fill="none" points="67,68 77,58 87,68 77,78 67,68" stroke="#000000" stroke-width="2"/>
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<polyline fill="none" points="67,79 87,79" stroke="#000000" stroke-width="2"/>
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<circ-port height="8" pin="90,80" width="8" x="56" y="66"/>
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<circ-port height="10" pin="130,80" width="10" x="125" y="65"/>
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<circ-anchor facing="east" height="6" width="6" x="87" y="67"/>
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</appear>
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<wire from="(120,80)" to="(130,80)"/>
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<wire from="(90,80)" to="(100,80)"/>
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<comp lib="0" loc="(130,80)" name="Pin">
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<a name="facing" val="west"/>
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<a name="output" val="true"/>
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<a name="labelloc" val="east"/>
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</comp>
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<comp lib="0" loc="(90,80)" name="Pin">
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<a name="tristate" val="false"/>
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</comp>
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<comp lib="1" loc="(120,80)" name="NOT Gate">
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<a name="size" val="20"/>
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<a name="out" val="0Z"/>
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</comp>
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</circuit>
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</project>
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