111 lines
3.8 KiB
XML
111 lines
3.8 KiB
XML
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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<project source="3.9.0" version="1.0">
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This file is intended to be loaded by Logisim-evolution v3.9.0(https://github.com/logisim-evolution/).
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<lib desc="#Wiring" name="0">
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<tool name="Pin">
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<a name="appearance" val="classic"/>
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</tool>
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</lib>
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<lib desc="#Gates" name="1"/>
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<lib desc="#Plexers" name="2"/>
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<lib desc="#Arithmetic" name="3"/>
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<lib desc="#Memory" name="4"/>
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<lib desc="#I/O" name="5"/>
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<lib desc="#TTL" name="6"/>
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<lib desc="#TCL" name="7"/>
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<lib desc="#Base" name="8"/>
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<lib desc="#BFH-Praktika" name="9"/>
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<lib desc="#Input/Output-Extra" name="10"/>
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<lib desc="#Soc" name="11"/>
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<main name="main"/>
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<options>
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<a name="gateUndefined" val="ignore"/>
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<a name="simlimit" val="1000"/>
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<a name="simrand" val="0"/>
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</options>
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<mappings>
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<tool lib="8" map="Button2" name="Poke Tool"/>
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<tool lib="8" map="Button3" name="Menu Tool"/>
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<tool lib="8" map="Ctrl Button1" name="Menu Tool"/>
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</mappings>
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<toolbar>
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<tool lib="8" name="Poke Tool"/>
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<tool lib="8" name="Edit Tool"/>
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<tool lib="8" name="Wiring Tool"/>
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<tool lib="8" name="Text Tool"/>
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<sep/>
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<tool lib="0" name="Pin"/>
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<tool lib="0" name="Pin">
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<a name="facing" val="west"/>
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<a name="output" val="true"/>
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</tool>
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<sep/>
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<tool lib="1" name="NOT Gate"/>
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<tool lib="1" name="AND Gate"/>
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<tool lib="1" name="OR Gate"/>
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<tool lib="1" name="XOR Gate"/>
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<tool lib="1" name="NAND Gate"/>
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<tool lib="1" name="NOR Gate"/>
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<sep/>
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<tool lib="4" name="D Flip-Flop"/>
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<tool lib="4" name="Register"/>
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</toolbar>
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<circuit name="main">
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<a name="appearance" val="logisim_evolution"/>
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<a name="circuit" val="main"/>
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<a name="circuitnamedboxfixedsize" val="true"/>
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<a name="simulationFrequency" val="1.0"/>
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<comp lib="0" loc="(110,240)" name="Pin">
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<a name="appearance" val="NewPins"/>
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<a name="label" val="B"/>
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</comp>
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<comp lib="0" loc="(110,300)" name="Pin">
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<a name="appearance" val="NewPins"/>
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<a name="label" val="C"/>
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</comp>
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<comp lib="0" loc="(110,360)" name="Pin">
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<a name="appearance" val="NewPins"/>
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<a name="label" val="A"/>
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</comp>
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<comp lib="0" loc="(110,420)" name="Pin">
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<a name="appearance" val="NewPins"/>
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<a name="label" val="D"/>
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</comp>
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<comp lib="0" loc="(500,340)" name="Pin">
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<a name="appearance" val="NewPins"/>
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<a name="facing" val="west"/>
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<a name="label" val="F"/>
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<a name="output" val="true"/>
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</comp>
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<comp lib="1" loc="(300,270)" name="NAND Gate">
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<a name="inputs" val="3"/>
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</comp>
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<comp lib="1" loc="(300,420)" name="NAND Gate"/>
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<comp lib="1" loc="(440,340)" name="NAND Gate"/>
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<wire from="(110,240)" to="(190,240)"/>
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<wire from="(110,300)" to="(190,300)"/>
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<wire from="(110,360)" to="(150,360)"/>
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<wire from="(110,420)" to="(150,420)"/>
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<wire from="(150,330)" to="(150,360)"/>
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<wire from="(150,330)" to="(210,330)"/>
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<wire from="(150,360)" to="(150,400)"/>
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<wire from="(150,400)" to="(240,400)"/>
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<wire from="(150,420)" to="(150,440)"/>
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<wire from="(150,440)" to="(240,440)"/>
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<wire from="(190,240)" to="(190,250)"/>
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<wire from="(190,250)" to="(240,250)"/>
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<wire from="(190,270)" to="(190,300)"/>
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<wire from="(190,270)" to="(240,270)"/>
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<wire from="(210,290)" to="(210,330)"/>
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<wire from="(210,290)" to="(240,290)"/>
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<wire from="(300,270)" to="(330,270)"/>
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<wire from="(300,420)" to="(330,420)"/>
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<wire from="(330,270)" to="(330,320)"/>
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<wire from="(330,320)" to="(380,320)"/>
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<wire from="(330,360)" to="(330,420)"/>
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<wire from="(330,360)" to="(380,360)"/>
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<wire from="(440,340)" to="(500,340)"/>
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</circuit>
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</project>
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