hardware/Logisim/Chatper7_hw1_C1C2/count_out.vcd

$date
	Fri May 30 08:26:55 2025
$end
$version
	Icarus Verilog
$end
$timescale
	1ns
$end
$scope module main $end
$var wire 1 ! q1_m4 $end
$var wire 1 " q1_m3 $end
$var wire 1 # q1 $end
$var wire 1 $ q0_m4 $end
$var wire 1 % q0_m3 $end
$var wire 1 & q0 $end
$var reg 1 ' c1 $end
$var reg 1 ( c2 $end
$var reg 1 ) clk $end
$var reg 1 * rst_n $end
$scope module u_mode3 $end
$var wire 1 ( c2 $end
$var wire 1 ) clk $end
$var wire 1 + d0i $end
$var wire 1 , d1i $end
$var wire 1 % q0 $end
$var wire 1 " q1 $end
$var wire 1 * rst_n $end
$var wire 1 - q1i $end
$var wire 1 . q0i $end
$scope module dd0 $end
$var wire 1 ) clk $end
$var wire 1 + d $end
$var wire 1 * rst_n $end
$var reg 1 . q $end
$upscope $end
$scope module dd1 $end
$var wire 1 ) clk $end
$var wire 1 , d $end
$var wire 1 * rst_n $end
$var reg 1 - q $end
$upscope $end
$upscope $end
$scope module u_mode4 $end
$var wire 1 ( c2 $end
$var wire 1 ) clk $end
$var wire 1 / d0i $end
$var wire 1 0 d1i $end
$var wire 1 $ q0 $end
$var wire 1 ! q1 $end
$var wire 1 * rst_n $end
$var wire 1 1 q1i $end
$var wire 1 2 q0i $end
$scope module dd0 $end
$var wire 1 ) clk $end
$var wire 1 / d $end
$var wire 1 * rst_n $end
$var reg 1 2 q $end
$upscope $end
$scope module dd1 $end
$var wire 1 ) clk $end
$var wire 1 0 d $end
$var wire 1 * rst_n $end
$var reg 1 1 q $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
$end
#0
$dumpvars
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