hardware/Logisim/Project_Car_Light/Light_wave.vcd

$date
	Thu May 29 10:38:34 2025
$end
$version
	Icarus Verilog
$end
$timescale
	1ns
$end
$scope module test $end
$var wire 1 ! q3 $end
$var wire 1 " q2 $end
$var wire 1 # q1 $end
$var reg 1 $ a $end
$var reg 1 % clk $end
$scope module uut $end
$var wire 1 $ a $end
$var wire 1 % clk $end
$var wire 1 # q1 $end
$var wire 1 " q2 $end
$var wire 1 ! q3 $end
$var wire 1 & t1 $end
$var wire 1 ' t2 $end
$var wire 1 ( t3 $end
$var wire 1 ) q3internal $end
$var wire 1 * q2internal $end
$var wire 1 + q1internal $end
$scope module dt1 $end
$var wire 1 & D0 $end
$var wire 1 % clk $end
$var reg 1 + Q0 $end
$upscope $end
$scope module dt2 $end
$var wire 1 ' D0 $end
$var wire 1 % clk $end
$var reg 1 * Q0 $end
$upscope $end
$scope module dt3 $end
$var wire 1 ( D0 $end
$var wire 1 % clk $end
$var reg 1 ) Q0 $end
$upscope $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
$end
#0
$dumpvars
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$end
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