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hardware/Verilog/test/tb_.vcd
2025-12-31 19:35:06 +08:00

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$date
Thu May 29 10:04:23 2025
$end
$version
Icarus Verilog
$end
$timescale
1ns
$end
$scope module tb_ $end
$var wire 1 ! c $end
$var reg 1 " a $end
$var reg 1 # b $end
$scope module test $end
$var wire 1 " a $end
$var wire 1 # b $end
$var wire 1 ! c $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
$end
#0
$dumpvars
0#
0"
0!
$end
#10
1#
#20
0#
1"
#30
1!
1#
#40