22 lines
628 B
Verilog
22 lines
628 B
Verilog
module pwm (
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input wire clk, // 时钟输入
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input wire rst, // 异步复位
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input wire [7:0] duty, // 占空比（0~255）
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output reg pwm_out // 输出信号
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);
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reg [7:0] counter = 0; // 8位计数器，周期为 256
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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counter <= 0;
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pwm_out <= 0;
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end else begin
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counter <= counter + 1;
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// 比较占空比设置
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if (counter < duty)
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pwm_out <= 1;
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else
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pwm_out <= 0;
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end
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end
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endmodule |