47 lines
527 B
Verilog
47 lines
527 B
Verilog
`timescale 10ns/1ns
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module and_door (
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input a,
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input b,
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output c
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);
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assign c = a&b;
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endmodule
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module tb_;
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reg a,b;
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wire c;
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and_door test(
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.a (a),
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.b (b),
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.c (c)
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);
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initial begin
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$dumpfile("tb_.vcd");
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$dumpvars(0, tb_);
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end
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initial begin
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a = 1'b0;
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b = 1'b0;
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#1;
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$display("%d",c);
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a = 1'b0;
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b = 1'b1;
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#1;
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$display("%d",c);
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a = 1'b1;
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b = 1'b0;
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#1;
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$display("%d",c);
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a = 1'b1;
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b = 1'b1;
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#1;
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$display("%d",c);
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end
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endmodule |