36 lines
677 B
Verilog
36 lines
677 B
Verilog
module pwm_tb;
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reg clk = 0;
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reg rst = 0;
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reg [7:0] duty = 128; // 默认占空比50%
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wire pwm_out;
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// 实例化
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pwm uut (
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.clk(clk),
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.rst(rst),
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.duty(duty),
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.pwm_out(pwm_out)
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);
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// 模拟时钟，每 10ns 反转一次，相当于 50MHz
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always #10 clk = ~clk;
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initial begin
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// 复位一段时间
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$dumpfile("wave.vcd");
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$dumpvars(0, pwm_tb);
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rst = 1;
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#20;
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rst = 0;
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// 运行一段时间后改变占空比
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#1000;
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duty = 64; // 25%
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#1000;
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duty = 192; // 75%
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#1000;
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$finish;
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end
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endmodule |