128 lines
2.0 KiB
Verilog
128 lines
2.0 KiB
Verilog
`timescale 10ns/1ns
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module DTouch (
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input clk,
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input rst_n,
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input d,
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output reg q
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);
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n)
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q <= 0; // 初始复位为 0
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else
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q <= d;
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end
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endmodule
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//when c1 = 0
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module mode3(
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input c2,
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input clk,
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input rst_n,
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output q1, q0
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);
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wire d0i, d1i;
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wire q0i, q1i;
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assign d1i = ((!q1i) && (!q0i) && c2) || ((!q1i) && (q0i) && (!c2));
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assign d0i = ((!q1i) && (!q0i) && (!c2)) || ((q1i) && (!q0i) && (c2)) ;
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DTouch dd0(.clk(clk), .rst_n(rst_n), .d(d0i), .q(q0i));
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DTouch dd1(.clk(clk), .rst_n(rst_n), .d(d1i), .q(q1i));
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assign q0 = q0i;
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assign q1 = q1i;
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endmodule
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//when c1 = 1
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module mode4(
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input c2,
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input clk,
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input rst_n,
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output q1, q0
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);
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wire d0i, d1i;
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wire q0i, q1i;
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assign d1i = ((!q1i) && (!q0i)) || ((q1i) && (q0i));
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assign d0i = ((q0i) && (!c2)) || ((!q0i) && (c2));
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DTouch dd0(.clk(clk), .rst_n(rst_n), .d(d0i), .q(q0i));
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DTouch dd1(.clk(clk), .rst_n(rst_n), .d(d1i), .q(q1i));
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assign q0 = q0i;
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assign q1 = q1i;
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endmodule
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module main;
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reg clk = 0;
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reg rst_n = 0;
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reg c1 = 0, c2 = 0;
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wire q1, q0;
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// 时钟生成
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always #2 clk = ~clk;
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// 实例化两个模块，但只选择一个输出
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wire q1_m3, q0_m3;
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wire q1_m4, q0_m4;
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mode3 u_mode3 (
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.c2(c2),
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.clk(clk),
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.rst_n(rst_n),
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.q1(q1_m3),
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.q0(q0_m3)
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);
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mode4 u_mode4 (
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.c2(c2),
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.clk(clk),
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.rst_n(rst_n),
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.q1(q1_m4),
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.q0(q0_m4)
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);
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// 根据 c1 选择哪个模块的输出
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assign q1 = (c1 == 0) ? q1_m3 : q1_m4;
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assign q0 = (c1 == 0) ? q0_m3 : q0_m4;
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// 测试输入控制
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initial begin
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$dumpfile("count_out.vcd");
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$dumpvars(0, main);
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// 添加复位：保持一段时间再释放
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rst_n = 0;
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#4 rst_n = 1;
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// 测试序列
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#4 c1 = 0; c2 = 0;
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#10 c2 = 1;
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#10 c2 = 0;
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#10 c2 = 1;
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#10 c2 = 0;
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#10 c1 = 1; c2 = 0;
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#10 c2 = 1;
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#10 c2 = 0;
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#10 c2 = 1;
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#10 c2 = 0;
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#20 $finish;
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end
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endmodule
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