62 lines
1.2 KiB
Verilog
62 lines
1.2 KiB
Verilog
`timescale 10ns/1ns
|
|
module D_Touch(
|
|
input D0,
|
|
input clk,
|
|
output reg Q0
|
|
);
|
|
always @(posedge clk) begin
|
|
Q0 <= D0;
|
|
end
|
|
|
|
endmodule
|
|
|
|
module Light_Time (
|
|
input clk,
|
|
input a,
|
|
output q1,
|
|
output q2,
|
|
output q3
|
|
);
|
|
wire q1internal , q2internal , q3internal;
|
|
wire t1 , t2 , t3;
|
|
assign t1 = (!q1internal)&&(!q2internal)&&(!q3internal)&&a||(q1internal)&&(q2internal)&&a;
|
|
assign t2 = (!q1internal)&&(!q2internal)&&(!q3internal)&&a||(q1internal)&&(q2internal)&&(q3internal)&&a;
|
|
assign t3 = (!q1internal)&&(!q2internal)&&(!q3internal)&&a||(q1internal)&&(q2internal)&&(!q3internal)&&a;
|
|
D_Touch dt1(.D0(t1) , .clk(clk) , .Q0(q1internal));
|
|
D_Touch dt2(.D0(t2) , .clk(clk) , .Q0(q2internal));
|
|
D_Touch dt3(.D0(t3) , .clk(clk) , .Q0(q3internal));
|
|
|
|
assign q1 = q1internal;
|
|
assign q2 = q2internal;
|
|
assign q3 = q3internal;
|
|
|
|
endmodule
|
|
|
|
module test;
|
|
|
|
reg clk , a;
|
|
wire q1 , q2 , q3;
|
|
|
|
Light_Time uut (
|
|
.clk(clk),
|
|
.a(a),
|
|
.q1(q1),
|
|
.q2(q2),
|
|
.q3(q3)
|
|
);
|
|
|
|
always #2 clk = ~clk;
|
|
|
|
initial begin
|
|
clk = 0;
|
|
a = 0;
|
|
$dumpfile("Light_wave.vcd");
|
|
$dumpvars(0, test);
|
|
|
|
// 开始测试
|
|
#10 a = 1;
|
|
#100 a = 0;
|
|
#120 $finish;
|
|
end
|
|
|
|
endmodule |