38 lines
561 B
Verilog
38 lines
561 B
Verilog
`timescale 10ns/1ns
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module orDoor (
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input a,
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input b,
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output c
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);
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assign c = a || b;
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endmodule
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module test;
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reg a , b;
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wire c;
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orDoor nnt(
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.a(a),
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.b(b),
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.c(c)
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);
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initial begin
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$dumpfile("ez.vcd");
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$dumpvars(0 , test);
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#10 a = 0;b = 0;
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#10 $display("%d %d %d", a , b , c);
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#10 a = 0;b = 1;
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#10 $display("%d %d %d", a , b , c);
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#10
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a = 1;b = 0;
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#10 $display("%d %d %d", a , b , c);
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#10
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a = 1;b = 1;
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#10 $display("%d %d %d", a , b , c);
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end
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endmodule
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