30 lines
733 B
Verilog
30 lines
733 B
Verilog
//`include "test0.v"
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module test_and_gate;
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reg a, b; // 定义输入变量
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wire y; // 定义输出变量
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// 实例化与门模块
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and_gate uut (
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.a(a),
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.b(b),
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.y(y)
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);
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initial begin
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// dump VCD
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$dumpfile("and_gate.vcd");
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$dumpvars(0, test_and_gate);
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// 显示标题
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$display("a b | y");
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$display("---------");
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// 测试所有输入组合
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a = 0; b = 0; #1 $display("%b %b | %b", a, b, y);
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a = 0; b = 1; #1 $display("%b %b | %b", a, b, y);
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a = 1; b = 0; #1 $display("%b %b | %b", a, b, y);
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a = 1; b = 1; #1 $display("%b %b | %b", a, b, y);
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$finish;
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end
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endmodule
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