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Verilog/test/test0/and_gate.vcd

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+$date
+	Thu May 29 09:14:21 2025
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module test_and_gate $end
+$var wire 1 ! y $end
+$var reg 1 " a $end
+$var reg 1 # b $end
+$upscope $end
+$enddefinitions $end
+$comment Show the parameter values. $end
+$dumpall
+$end
+#0
+$dumpvars
+0#
+0"
+z!
+$end
+#1
+1#
+#2
+0#
+1"
+#3
+1#
+#4