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Verilog/test/test1/test1.needvvp

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+#! /c/Source/iverilog-install/bin/vvp
+:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision - 9;
+:vpi_module "D:\iverilog\lib\ivl\system.vpi";
+:vpi_module "D:\iverilog\lib\ivl\vhdl_sys.vpi";
+:vpi_module "D:\iverilog\lib\ivl\vhdl_textio.vpi";
+:vpi_module "D:\iverilog\lib\ivl\v2005_math.vpi";
+:vpi_module "D:\iverilog\lib\ivl\va_math.vpi";
+S_000001eb079d5100 .scope module, "tb_" "tb_" 2 12;
+ .timescale -8 -9;
+v000001eb07ab9700_0 .var "a", 0 0;
+v000001eb079d5420_0 .var "b", 0 0;
+v000001eb079d54c0_0 .net "c", 0 0, L_000001eb079a2da0;  1 drivers
+S_000001eb079d5290 .scope module, "test" "and_door" 2 17, 2 2 0, S_000001eb079d5100;
+ .timescale -8 -9;
+    .port_info 0 /INPUT 1 "a";
+    .port_info 1 /INPUT 1 "b";
+    .port_info 2 /OUTPUT 1 "c";
+L_000001eb079a2da0 .functor AND 1, v000001eb07ab9700_0, v000001eb079d5420_0, C4<1>, C4<1>;
+v000001eb079a2fc0_0 .net "a", 0 0, v000001eb07ab9700_0;  1 drivers
+v000001eb079a2b20_0 .net "b", 0 0, v000001eb079d5420_0;  1 drivers
+v000001eb079a31e0_0 .net "c", 0 0, L_000001eb079a2da0;  alias, 1 drivers
+    .scope S_000001eb079d5100;
+T_0 ;
+    %vpi_call 2 24 "$dumpfile", "tb_.vcd" {0 0 0};
+    %vpi_call 2 25 "$dumpvars", 32'sb00000000000000000000000000000000, S_000001eb079d5100 {0 0 0};
+    %end;
+    .thread T_0;
+    .scope S_000001eb079d5100;
+T_1 ;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001eb07ab9700_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001eb079d5420_0, 0, 1;
+    %delay 10, 0;
+    %vpi_call 2 32 "$display", "%d", v000001eb079d54c0_0 {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001eb07ab9700_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001eb079d5420_0, 0, 1;
+    %delay 10, 0;
+    %vpi_call 2 36 "$display", "%d", v000001eb079d54c0_0 {0 0 0};
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001eb07ab9700_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001eb079d5420_0, 0, 1;
+    %delay 10, 0;
+    %vpi_call 2 40 "$display", "%d", v000001eb079d54c0_0 {0 0 0};
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001eb07ab9700_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001eb079d5420_0, 0, 1;
+    %delay 10, 0;
+    %vpi_call 2 44 "$display", "%d", v000001eb079d54c0_0 {0 0 0};
+    %end;
+    .thread T_1;
+# The file index is used to find the file name in the following table.
+:file_names 3;
+    "N/A";
+    "<interactive>";
+    ".\test1\test1.v";

Verilog/test/test1/test1.v

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+`timescale 10ns/1ns
+module and_door (
+    input a,
+    input b,
+    output c
+);
+
+assign c = a&b;
+    
+endmodule
+
+module tb_;
+reg a,b;
+wire c;
+
+ 
+and_door test(
+    .a (a),
+    .b (b),
+    .c (c)
+);
+
+initial begin
+    $dumpfile("tb_.vcd");
+    $dumpvars(0, tb_);
+end
+
+initial begin
+    a = 1'b0;
+    b = 1'b0;
+    #1;
+    $display("%d",c);
+    a = 1'b0;
+    b = 1'b1;
+    #1;
+    $display("%d",c);
+    a = 1'b1;
+    b = 1'b0;
+    #1;
+    $display("%d",c);
+    a = 1'b1;
+    b = 1'b1;
+    #1;
+    $display("%d",c);
+end
+
+endmodule