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Verilog/test/test1/test1.v

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+`timescale 10ns/1ns
+module and_door (
+    input a,
+    input b,
+    output c
+);
+
+assign c = a&b;
+    
+endmodule
+
+module tb_;
+reg a,b;
+wire c;
+
+ 
+and_door test(
+    .a (a),
+    .b (b),
+    .c (c)
+);
+
+initial begin
+    $dumpfile("tb_.vcd");
+    $dumpvars(0, tb_);
+end
+
+initial begin
+    a = 1'b0;
+    b = 1'b0;
+    #1;
+    $display("%d",c);
+    a = 1'b0;
+    b = 1'b1;
+    #1;
+    $display("%d",c);
+    a = 1'b1;
+    b = 1'b0;
+    #1;
+    $display("%d",c);
+    a = 1'b1;
+    b = 1'b1;
+    #1;
+    $display("%d",c);
+end
+
+endmodule