New Hardware Git

Verilog/test/wave.vcd

@@ -0,0 +1,797 @@
+$date
+	Wed May 28 23:47:04 2025
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module pwm_tb $end
+$var wire 1 ! pwm_out $end
+$var reg 1 " clk $end
+$var reg 8 # duty [7:0] $end
+$var reg 1 $ rst $end
+$scope module uut $end
+$var wire 1 " clk $end
+$var wire 8 % duty [7:0] $end
+$var wire 1 $ rst $end
+$var reg 8 & counter [7:0] $end
+$var reg 1 ! pwm_out $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+$comment Show the parameter values. $end
+$dumpall
+$end
+#0
+$dumpvars
+b0 &
+b10000000 %
+1$
+b10000000 #
+0"
+0!
+$end
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