New Hardware Git
This commit is contained in:
e2hang
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Logisim/Project_Car_Light/1.jpg
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Logisim/Project_Car_Light/4.jpg
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Logisim/Project_Car_Light/5.mp4
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Logisim/Project_Car_Light/Car_Light.circ
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Logisim/Project_Car_Light/Car_Light.circ
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|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<project source="3.9.0" version="1.0">
|
||||
This file is intended to be loaded by Logisim-evolution v3.9.0(https://github.com/logisim-evolution/).
|
||||
|
||||
<lib desc="#Wiring" name="0">
|
||||
<tool name="Splitter">
|
||||
<a name="appear" val="center"/>
|
||||
<a name="fanout" val="6"/>
|
||||
<a name="incoming" val="6"/>
|
||||
</tool>
|
||||
<tool name="Pin">
|
||||
<a name="appearance" val="classic"/>
|
||||
<a name="output" val="true"/>
|
||||
</tool>
|
||||
<tool name="Pull Resistor">
|
||||
<a name="pull" val="1"/>
|
||||
</tool>
|
||||
</lib>
|
||||
<lib desc="#Gates" name="1">
|
||||
<tool name="OR Gate">
|
||||
<a name="size" val="30"/>
|
||||
</tool>
|
||||
<tool name="NAND Gate">
|
||||
<a name="size" val="30"/>
|
||||
</tool>
|
||||
<tool name="NOR Gate">
|
||||
<a name="inputs" val="6"/>
|
||||
</tool>
|
||||
</lib>
|
||||
<lib desc="#Plexers" name="2"/>
|
||||
<lib desc="#Arithmetic" name="3"/>
|
||||
<lib desc="#Memory" name="4"/>
|
||||
<lib desc="#I/O" name="5"/>
|
||||
<lib desc="#TTL" name="6"/>
|
||||
<lib desc="#TCL" name="7"/>
|
||||
<lib desc="#Base" name="8">
|
||||
<tool name="Text Tool">
|
||||
<a name="font" val="SansSerif plain 12"/>
|
||||
</tool>
|
||||
</lib>
|
||||
<lib desc="#BFH-Praktika" name="9"/>
|
||||
<lib desc="#Input/Output-Extra" name="10"/>
|
||||
<lib desc="#Soc" name="11"/>
|
||||
<lib desc="file#..\7400-logisim-main\circ\pulse.circ" name="12"/>
|
||||
<main name="main"/>
|
||||
<options>
|
||||
<a name="gateUndefined" val="ignore"/>
|
||||
<a name="simlimit" val="1000"/>
|
||||
<a name="simrand" val="0"/>
|
||||
</options>
|
||||
<mappings>
|
||||
<tool lib="8" map="Button2" name="Poke Tool"/>
|
||||
<tool lib="8" map="Button3" name="Menu Tool"/>
|
||||
<tool lib="8" map="Ctrl Button1" name="Menu Tool"/>
|
||||
</mappings>
|
||||
<toolbar>
|
||||
<tool lib="8" name="Poke Tool"/>
|
||||
<tool lib="8" name="Edit Tool"/>
|
||||
<tool lib="8" name="Wiring Tool"/>
|
||||
<tool lib="8" name="Text Tool">
|
||||
<a name="font" val="SansSerif plain 12"/>
|
||||
</tool>
|
||||
<sep/>
|
||||
<tool lib="0" name="Pin"/>
|
||||
<tool lib="0" name="Pin">
|
||||
<a name="facing" val="west"/>
|
||||
<a name="output" val="true"/>
|
||||
</tool>
|
||||
<sep/>
|
||||
<tool lib="1" name="NOT Gate"/>
|
||||
<tool lib="1" name="AND Gate"/>
|
||||
<tool lib="1" name="OR Gate"/>
|
||||
<tool lib="1" name="XOR Gate"/>
|
||||
<tool lib="1" name="NAND Gate"/>
|
||||
<tool lib="1" name="NOR Gate"/>
|
||||
<sep/>
|
||||
<tool lib="4" name="D Flip-Flop"/>
|
||||
<tool lib="4" name="Register"/>
|
||||
</toolbar>
|
||||
<circuit name="main">
|
||||
<a name="appearance" val="logisim_evolution"/>
|
||||
<a name="circuit" val="main"/>
|
||||
<a name="circuitnamedboxfixedsize" val="true"/>
|
||||
<a name="simulationFrequency" val="1.0"/>
|
||||
<comp lib="0" loc="(200,480)" name="Clock">
|
||||
<a name="facing" val="north"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(1070,590)" name="OR Gate">
|
||||
<a name="facing" val="south"/>
|
||||
<a name="size" val="30"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(1110,800)" name="NOT Gate"/>
|
||||
<comp lib="1" loc="(1130,590)" name="OR Gate">
|
||||
<a name="facing" val="south"/>
|
||||
<a name="size" val="30"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(1190,590)" name="OR Gate">
|
||||
<a name="facing" val="south"/>
|
||||
<a name="size" val="30"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(1230,490)" name="NOT Gate">
|
||||
<a name="facing" val="north"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(1240,460)" name="AND Gate">
|
||||
<a name="facing" val="north"/>
|
||||
<a name="size" val="30"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(1250,880)" name="AND Gate">
|
||||
<a name="inputs" val="3"/>
|
||||
<a name="size" val="70"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(1400,240)" name="AND Gate">
|
||||
<a name="inputs" val="3"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(1400,350)" name="AND Gate">
|
||||
<a name="inputs" val="4"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(1540,170)" name="AND Gate"/>
|
||||
<comp lib="1" loc="(1540,360)" name="AND Gate"/>
|
||||
<comp lib="1" loc="(160,140)" name="OR Gate">
|
||||
<a name="label" val="D1"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(160,220)" name="OR Gate">
|
||||
<a name="label" val="D2"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(160,300)" name="OR Gate">
|
||||
<a name="label" val="D3"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(170,570)" name="OR Gate">
|
||||
<a name="inputs" val="3"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(240,640)" name="AND Gate">
|
||||
<a name="label" val="F501"/>
|
||||
<a name="size" val="30"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(270,820)" name="NOT Gate">
|
||||
<a name="facing" val="west"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(280,590)" name="OR Gate">
|
||||
<a name="facing" val="south"/>
|
||||
<a name="size" val="30"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(340,590)" name="OR Gate">
|
||||
<a name="facing" val="south"/>
|
||||
<a name="size" val="30"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(400,590)" name="OR Gate">
|
||||
<a name="facing" val="south"/>
|
||||
<a name="size" val="30"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(440,490)" name="NOT Gate">
|
||||
<a name="facing" val="north"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(450,460)" name="AND Gate">
|
||||
<a name="facing" val="north"/>
|
||||
<a name="size" val="30"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(580,1050)" name="AND Gate">
|
||||
<a name="facing" val="south"/>
|
||||
<a name="inputs" val="3"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(590,660)" name="NOT Gate"/>
|
||||
<comp lib="1" loc="(610,240)" name="AND Gate">
|
||||
<a name="inputs" val="3"/>
|
||||
<a name="label" val="Q1Q2X"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(610,350)" name="AND Gate">
|
||||
<a name="inputs" val="4"/>
|
||||
<a name="label" val="nQ1nQ2nQ3X"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(660,780)" name="XOR Gate">
|
||||
<a name="facing" val="south"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(680,860)" name="OR Gate">
|
||||
<a name="facing" val="south"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(730,790)" name="AND Gate">
|
||||
<a name="facing" val="south"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(750,170)" name="AND Gate">
|
||||
<a name="label" val="Q1Q2Q3X"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(750,360)" name="AND Gate">
|
||||
<a name="label" val="Q1Q2nQ3X"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(770,660)" name="NOT Gate">
|
||||
<a name="facing" val="west"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(90,850)" name="AND Gate">
|
||||
<a name="facing" val="west"/>
|
||||
<a name="inputs" val="3"/>
|
||||
<a name="size" val="70"/>
|
||||
</comp>
|
||||
<comp lib="1" loc="(950,140)" name="OR Gate"/>
|
||||
<comp lib="1" loc="(950,220)" name="OR Gate"/>
|
||||
<comp lib="1" loc="(950,300)" name="OR Gate"/>
|
||||
<comp lib="1" loc="(990,580)" name="OR Gate">
|
||||
<a name="inputs" val="3"/>
|
||||
</comp>
|
||||
<comp lib="4" loc="(1050,130)" name="D Flip-Flop">
|
||||
<a name="appearance" val="logisim_evolution"/>
|
||||
</comp>
|
||||
<comp lib="4" loc="(1050,210)" name="D Flip-Flop">
|
||||
<a name="appearance" val="logisim_evolution"/>
|
||||
</comp>
|
||||
<comp lib="4" loc="(1050,290)" name="D Flip-Flop">
|
||||
<a name="appearance" val="logisim_evolution"/>
|
||||
</comp>
|
||||
<comp lib="4" loc="(260,130)" name="D Flip-Flop">
|
||||
<a name="appearance" val="logisim_evolution"/>
|
||||
<a name="label" val="Q1"/>
|
||||
</comp>
|
||||
<comp lib="4" loc="(260,210)" name="D Flip-Flop">
|
||||
<a name="appearance" val="logisim_evolution"/>
|
||||
<a name="label" val="Q2"/>
|
||||
</comp>
|
||||
<comp lib="4" loc="(260,290)" name="D Flip-Flop">
|
||||
<a name="appearance" val="logisim_evolution"/>
|
||||
<a name="label" val="Q3"/>
|
||||
</comp>
|
||||
<comp lib="5" loc="(1070,610)" name="LED">
|
||||
<a name="facing" val="north"/>
|
||||
</comp>
|
||||
<comp lib="5" loc="(1130,610)" name="LED">
|
||||
<a name="facing" val="north"/>
|
||||
</comp>
|
||||
<comp lib="5" loc="(1190,610)" name="LED">
|
||||
<a name="facing" val="north"/>
|
||||
</comp>
|
||||
<comp lib="5" loc="(1250,680)" name="Button">
|
||||
<a name="facing" val="north"/>
|
||||
<a name="label" val="Right"/>
|
||||
</comp>
|
||||
<comp lib="5" loc="(280,610)" name="LED">
|
||||
<a name="facing" val="north"/>
|
||||
</comp>
|
||||
<comp lib="5" loc="(340,1150)" name="Button">
|
||||
<a name="facing" val="north"/>
|
||||
<a name="label" val="Stop"/>
|
||||
</comp>
|
||||
<comp lib="5" loc="(340,610)" name="LED">
|
||||
<a name="facing" val="north"/>
|
||||
</comp>
|
||||
<comp lib="5" loc="(400,610)" name="LED">
|
||||
<a name="facing" val="north"/>
|
||||
</comp>
|
||||
<comp lib="5" loc="(460,680)" name="Button">
|
||||
<a name="facing" val="north"/>
|
||||
<a name="label" val="Left"/>
|
||||
</comp>
|
||||
<comp lib="5" loc="(70,970)" name="Button">
|
||||
<a name="label" val="Brake"/>
|
||||
</comp>
|
||||
<wire from="(1010,660)" to="(1010,800)"/>
|
||||
<wire from="(1010,660)" to="(1250,660)"/>
|
||||
<wire from="(1010,800)" to="(1080,800)"/>
|
||||
<wire from="(1030,540)" to="(1030,580)"/>
|
||||
<wire from="(1030,540)" to="(1060,540)"/>
|
||||
<wire from="(1060,540)" to="(1060,560)"/>
|
||||
<wire from="(1060,540)" to="(1120,540)"/>
|
||||
<wire from="(1070,590)" to="(1070,610)"/>
|
||||
<wire from="(1080,470)" to="(1080,560)"/>
|
||||
<wire from="(1080,470)" to="(1120,470)"/>
|
||||
<wire from="(1100,140)" to="(1160,140)"/>
|
||||
<wire from="(1100,180)" to="(1270,180)"/>
|
||||
<wire from="(1100,220)" to="(1140,220)"/>
|
||||
<wire from="(1100,260)" to="(1260,260)"/>
|
||||
<wire from="(1100,300)" to="(1120,300)"/>
|
||||
<wire from="(1100,340)" to="(1250,340)"/>
|
||||
<wire from="(1110,800)" to="(1180,800)"/>
|
||||
<wire from="(1120,300)" to="(1120,470)"/>
|
||||
<wire from="(1120,300)" to="(1470,300)"/>
|
||||
<wire from="(1120,540)" to="(1120,560)"/>
|
||||
<wire from="(1120,540)" to="(1180,540)"/>
|
||||
<wire from="(1130,590)" to="(1130,610)"/>
|
||||
<wire from="(1130,910)" to="(1130,970)"/>
|
||||
<wire from="(1130,910)" to="(1180,910)"/>
|
||||
<wire from="(1140,220)" to="(1140,560)"/>
|
||||
<wire from="(1140,220)" to="(1180,220)"/>
|
||||
<wire from="(1160,140)" to="(1160,470)"/>
|
||||
<wire from="(1160,140)" to="(1280,140)"/>
|
||||
<wire from="(1160,470)" to="(1200,470)"/>
|
||||
<wire from="(1180,220)" to="(1180,240)"/>
|
||||
<wire from="(1180,240)" to="(1350,240)"/>
|
||||
<wire from="(1180,540)" to="(1180,560)"/>
|
||||
<wire from="(1180,540)" to="(1230,540)"/>
|
||||
<wire from="(1180,800)" to="(1180,850)"/>
|
||||
<wire from="(1180,870)" to="(1180,880)"/>
|
||||
<wire from="(1190,590)" to="(1190,610)"/>
|
||||
<wire from="(1200,470)" to="(1200,560)"/>
|
||||
<wire from="(1230,520)" to="(1230,540)"/>
|
||||
<wire from="(1240,450)" to="(1240,460)"/>
|
||||
<wire from="(1240,450)" to="(1250,450)"/>
|
||||
<wire from="(1250,340)" to="(1250,360)"/>
|
||||
<wire from="(1250,360)" to="(1320,360)"/>
|
||||
<wire from="(1250,370)" to="(1250,450)"/>
|
||||
<wire from="(1250,370)" to="(1300,370)"/>
|
||||
<wire from="(1250,490)" to="(1250,660)"/>
|
||||
<wire from="(1250,660)" to="(1250,680)"/>
|
||||
<wire from="(1250,880)" to="(1250,1070)"/>
|
||||
<wire from="(1260,260)" to="(1260,340)"/>
|
||||
<wire from="(1260,340)" to="(1350,340)"/>
|
||||
<wire from="(1270,180)" to="(1270,330)"/>
|
||||
<wire from="(1270,330)" to="(1350,330)"/>
|
||||
<wire from="(1280,140)" to="(1280,220)"/>
|
||||
<wire from="(1280,220)" to="(1350,220)"/>
|
||||
<wire from="(1300,260)" to="(1300,370)"/>
|
||||
<wire from="(1300,260)" to="(1350,260)"/>
|
||||
<wire from="(1300,370)" to="(1350,370)"/>
|
||||
<wire from="(1320,360)" to="(1320,380)"/>
|
||||
<wire from="(1320,360)" to="(1350,360)"/>
|
||||
<wire from="(1320,380)" to="(1490,380)"/>
|
||||
<wire from="(1400,240)" to="(1430,240)"/>
|
||||
<wire from="(1400,350)" to="(1410,350)"/>
|
||||
<wire from="(1410,20)" to="(1410,350)"/>
|
||||
<wire from="(1430,160)" to="(1430,240)"/>
|
||||
<wire from="(1430,160)" to="(1470,160)"/>
|
||||
<wire from="(1430,240)" to="(1430,340)"/>
|
||||
<wire from="(1430,340)" to="(1490,340)"/>
|
||||
<wire from="(1430,50)" to="(1430,160)"/>
|
||||
<wire from="(1470,150)" to="(1470,160)"/>
|
||||
<wire from="(1470,150)" to="(1490,150)"/>
|
||||
<wire from="(1470,190)" to="(1470,300)"/>
|
||||
<wire from="(1470,190)" to="(1490,190)"/>
|
||||
<wire from="(1540,100)" to="(1540,170)"/>
|
||||
<wire from="(1540,360)" to="(1540,390)"/>
|
||||
<wire from="(160,140)" to="(250,140)"/>
|
||||
<wire from="(160,220)" to="(250,220)"/>
|
||||
<wire from="(160,300)" to="(250,300)"/>
|
||||
<wire from="(160,820)" to="(270,820)"/>
|
||||
<wire from="(160,850)" to="(190,850)"/>
|
||||
<wire from="(160,880)" to="(190,880)"/>
|
||||
<wire from="(170,540)" to="(170,570)"/>
|
||||
<wire from="(170,540)" to="(270,540)"/>
|
||||
<wire from="(170,570)" to="(170,630)"/>
|
||||
<wire from="(170,630)" to="(210,630)"/>
|
||||
<wire from="(190,850)" to="(190,870)"/>
|
||||
<wire from="(190,870)" to="(680,870)"/>
|
||||
<wire from="(190,880)" to="(190,930)"/>
|
||||
<wire from="(190,930)" to="(290,930)"/>
|
||||
<wire from="(200,180)" to="(200,260)"/>
|
||||
<wire from="(200,180)" to="(250,180)"/>
|
||||
<wire from="(200,260)" to="(200,340)"/>
|
||||
<wire from="(200,260)" to="(250,260)"/>
|
||||
<wire from="(200,340)" to="(200,430)"/>
|
||||
<wire from="(200,340)" to="(250,340)"/>
|
||||
<wire from="(200,430)" to="(200,480)"/>
|
||||
<wire from="(200,430)" to="(990,430)"/>
|
||||
<wire from="(270,540)" to="(270,560)"/>
|
||||
<wire from="(270,540)" to="(330,540)"/>
|
||||
<wire from="(280,590)" to="(280,610)"/>
|
||||
<wire from="(290,470)" to="(290,560)"/>
|
||||
<wire from="(290,470)" to="(330,470)"/>
|
||||
<wire from="(290,930)" to="(290,970)"/>
|
||||
<wire from="(290,970)" to="(580,970)"/>
|
||||
<wire from="(30,1120)" to="(340,1120)"/>
|
||||
<wire from="(30,550)" to="(120,550)"/>
|
||||
<wire from="(30,550)" to="(30,650)"/>
|
||||
<wire from="(30,650)" to="(210,650)"/>
|
||||
<wire from="(30,650)" to="(30,1120)"/>
|
||||
<wire from="(300,820)" to="(520,820)"/>
|
||||
<wire from="(310,140)" to="(370,140)"/>
|
||||
<wire from="(310,180)" to="(480,180)"/>
|
||||
<wire from="(310,220)" to="(350,220)"/>
|
||||
<wire from="(310,260)" to="(470,260)"/>
|
||||
<wire from="(310,300)" to="(330,300)"/>
|
||||
<wire from="(310,340)" to="(460,340)"/>
|
||||
<wire from="(330,300)" to="(330,470)"/>
|
||||
<wire from="(330,300)" to="(680,300)"/>
|
||||
<wire from="(330,540)" to="(330,560)"/>
|
||||
<wire from="(330,540)" to="(390,540)"/>
|
||||
<wire from="(340,1110)" to="(340,1120)"/>
|
||||
<wire from="(340,1110)" to="(860,1110)"/>
|
||||
<wire from="(340,1120)" to="(340,1150)"/>
|
||||
<wire from="(340,590)" to="(340,610)"/>
|
||||
<wire from="(350,220)" to="(350,560)"/>
|
||||
<wire from="(350,220)" to="(390,220)"/>
|
||||
<wire from="(370,140)" to="(370,470)"/>
|
||||
<wire from="(370,140)" to="(490,140)"/>
|
||||
<wire from="(370,470)" to="(410,470)"/>
|
||||
<wire from="(390,220)" to="(390,240)"/>
|
||||
<wire from="(390,240)" to="(560,240)"/>
|
||||
<wire from="(390,540)" to="(390,560)"/>
|
||||
<wire from="(390,540)" to="(440,540)"/>
|
||||
<wire from="(400,590)" to="(400,610)"/>
|
||||
<wire from="(410,470)" to="(410,560)"/>
|
||||
<wire from="(440,520)" to="(440,540)"/>
|
||||
<wire from="(450,450)" to="(450,460)"/>
|
||||
<wire from="(450,450)" to="(460,450)"/>
|
||||
<wire from="(460,340)" to="(460,360)"/>
|
||||
<wire from="(460,360)" to="(530,360)"/>
|
||||
<wire from="(460,370)" to="(460,450)"/>
|
||||
<wire from="(460,370)" to="(510,370)"/>
|
||||
<wire from="(460,490)" to="(460,660)"/>
|
||||
<wire from="(460,660)" to="(460,680)"/>
|
||||
<wire from="(460,660)" to="(520,660)"/>
|
||||
<wire from="(470,260)" to="(470,340)"/>
|
||||
<wire from="(470,340)" to="(560,340)"/>
|
||||
<wire from="(480,180)" to="(480,330)"/>
|
||||
<wire from="(480,330)" to="(560,330)"/>
|
||||
<wire from="(490,140)" to="(490,220)"/>
|
||||
<wire from="(490,220)" to="(560,220)"/>
|
||||
<wire from="(50,160)" to="(110,160)"/>
|
||||
<wire from="(50,160)" to="(50,200)"/>
|
||||
<wire from="(50,20)" to="(50,160)"/>
|
||||
<wire from="(50,20)" to="(620,20)"/>
|
||||
<wire from="(50,200)" to="(110,200)"/>
|
||||
<wire from="(50,200)" to="(50,280)"/>
|
||||
<wire from="(50,280)" to="(110,280)"/>
|
||||
<wire from="(50,320)" to="(110,320)"/>
|
||||
<wire from="(50,320)" to="(50,390)"/>
|
||||
<wire from="(50,390)" to="(750,390)"/>
|
||||
<wire from="(510,260)" to="(510,370)"/>
|
||||
<wire from="(510,260)" to="(560,260)"/>
|
||||
<wire from="(510,370)" to="(560,370)"/>
|
||||
<wire from="(520,660)" to="(520,820)"/>
|
||||
<wire from="(520,660)" to="(540,660)"/>
|
||||
<wire from="(530,360)" to="(530,380)"/>
|
||||
<wire from="(530,360)" to="(560,360)"/>
|
||||
<wire from="(530,380)" to="(700,380)"/>
|
||||
<wire from="(540,660)" to="(540,990)"/>
|
||||
<wire from="(540,660)" to="(560,660)"/>
|
||||
<wire from="(540,990)" to="(560,990)"/>
|
||||
<wire from="(560,990)" to="(560,1000)"/>
|
||||
<wire from="(580,1050)" to="(900,1050)"/>
|
||||
<wire from="(580,970)" to="(1130,970)"/>
|
||||
<wire from="(580,970)" to="(580,1000)"/>
|
||||
<wire from="(590,660)" to="(640,660)"/>
|
||||
<wire from="(600,990)" to="(600,1000)"/>
|
||||
<wire from="(600,990)" to="(820,990)"/>
|
||||
<wire from="(610,240)" to="(640,240)"/>
|
||||
<wire from="(610,350)" to="(620,350)"/>
|
||||
<wire from="(620,20)" to="(620,350)"/>
|
||||
<wire from="(640,160)" to="(640,240)"/>
|
||||
<wire from="(640,160)" to="(680,160)"/>
|
||||
<wire from="(640,240)" to="(640,340)"/>
|
||||
<wire from="(640,340)" to="(700,340)"/>
|
||||
<wire from="(640,50)" to="(640,160)"/>
|
||||
<wire from="(640,660)" to="(640,700)"/>
|
||||
<wire from="(640,700)" to="(640,720)"/>
|
||||
<wire from="(640,700)" to="(710,700)"/>
|
||||
<wire from="(660,780)" to="(660,810)"/>
|
||||
<wire from="(680,150)" to="(680,160)"/>
|
||||
<wire from="(680,150)" to="(700,150)"/>
|
||||
<wire from="(680,190)" to="(680,300)"/>
|
||||
<wire from="(680,190)" to="(700,190)"/>
|
||||
<wire from="(680,660)" to="(680,680)"/>
|
||||
<wire from="(680,660)" to="(770,660)"/>
|
||||
<wire from="(680,680)" to="(680,720)"/>
|
||||
<wire from="(680,680)" to="(750,680)"/>
|
||||
<wire from="(680,860)" to="(680,870)"/>
|
||||
<wire from="(680,870)" to="(1180,870)"/>
|
||||
<wire from="(70,120)" to="(110,120)"/>
|
||||
<wire from="(70,50)" to="(640,50)"/>
|
||||
<wire from="(70,50)" to="(70,120)"/>
|
||||
<wire from="(70,970)" to="(290,970)"/>
|
||||
<wire from="(700,790)" to="(700,810)"/>
|
||||
<wire from="(700,790)" to="(730,790)"/>
|
||||
<wire from="(710,700)" to="(710,740)"/>
|
||||
<wire from="(750,100)" to="(750,170)"/>
|
||||
<wire from="(750,360)" to="(750,390)"/>
|
||||
<wire from="(750,680)" to="(750,740)"/>
|
||||
<wire from="(80,100)" to="(750,100)"/>
|
||||
<wire from="(80,100)" to="(80,240)"/>
|
||||
<wire from="(80,1050)" to="(580,1050)"/>
|
||||
<wire from="(80,240)" to="(110,240)"/>
|
||||
<wire from="(80,570)" to="(120,570)"/>
|
||||
<wire from="(80,570)" to="(80,1050)"/>
|
||||
<wire from="(800,660)" to="(820,660)"/>
|
||||
<wire from="(820,660)" to="(1010,660)"/>
|
||||
<wire from="(820,660)" to="(820,990)"/>
|
||||
<wire from="(840,160)" to="(840,200)"/>
|
||||
<wire from="(840,160)" to="(900,160)"/>
|
||||
<wire from="(840,20)" to="(1410,20)"/>
|
||||
<wire from="(840,20)" to="(840,160)"/>
|
||||
<wire from="(840,200)" to="(840,280)"/>
|
||||
<wire from="(840,200)" to="(900,200)"/>
|
||||
<wire from="(840,280)" to="(900,280)"/>
|
||||
<wire from="(840,320)" to="(840,390)"/>
|
||||
<wire from="(840,320)" to="(900,320)"/>
|
||||
<wire from="(840,390)" to="(1540,390)"/>
|
||||
<wire from="(860,120)" to="(900,120)"/>
|
||||
<wire from="(860,50)" to="(1430,50)"/>
|
||||
<wire from="(860,50)" to="(860,120)"/>
|
||||
<wire from="(860,540)" to="(860,1110)"/>
|
||||
<wire from="(860,540)" to="(940,540)"/>
|
||||
<wire from="(870,100)" to="(1540,100)"/>
|
||||
<wire from="(870,100)" to="(870,240)"/>
|
||||
<wire from="(870,240)" to="(900,240)"/>
|
||||
<wire from="(90,590)" to="(120,590)"/>
|
||||
<wire from="(90,590)" to="(90,850)"/>
|
||||
<wire from="(900,580)" to="(900,1050)"/>
|
||||
<wire from="(900,580)" to="(940,580)"/>
|
||||
<wire from="(940,1070)" to="(1250,1070)"/>
|
||||
<wire from="(940,540)" to="(940,560)"/>
|
||||
<wire from="(940,600)" to="(940,1070)"/>
|
||||
<wire from="(950,140)" to="(1040,140)"/>
|
||||
<wire from="(950,220)" to="(1040,220)"/>
|
||||
<wire from="(950,300)" to="(1040,300)"/>
|
||||
<wire from="(990,180)" to="(1040,180)"/>
|
||||
<wire from="(990,180)" to="(990,260)"/>
|
||||
<wire from="(990,260)" to="(1040,260)"/>
|
||||
<wire from="(990,260)" to="(990,340)"/>
|
||||
<wire from="(990,340)" to="(1040,340)"/>
|
||||
<wire from="(990,340)" to="(990,430)"/>
|
||||
<wire from="(990,580)" to="(1030,580)"/>
|
||||
</circuit>
|
||||
</project>
|
||||
62
Logisim/Project_Car_Light/Car_Light.v
Normal file
62
Logisim/Project_Car_Light/Car_Light.v
Normal file
@@ -0,0 +1,62 @@
|
||||
`timescale 10ns/1ns
|
||||
module D_Touch(
|
||||
input D0,
|
||||
input clk,
|
||||
output reg Q0
|
||||
);
|
||||
always @(posedge clk) begin
|
||||
Q0 <= D0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
module Light_Time (
|
||||
input clk,
|
||||
input a,
|
||||
output q1,
|
||||
output q2,
|
||||
output q3
|
||||
);
|
||||
wire q1internal , q2internal , q3internal;
|
||||
wire t1 , t2 , t3;
|
||||
assign t1 = (!q1internal)&&(!q2internal)&&(!q3internal)&&a||(q1internal)&&(q2internal)&&a;
|
||||
assign t2 = (!q1internal)&&(!q2internal)&&(!q3internal)&&a||(q1internal)&&(q2internal)&&(q3internal)&&a;
|
||||
assign t3 = (!q1internal)&&(!q2internal)&&(!q3internal)&&a||(q1internal)&&(q2internal)&&(!q3internal)&&a;
|
||||
D_Touch dt1(.D0(t1) , .clk(clk) , .Q0(q1internal));
|
||||
D_Touch dt2(.D0(t2) , .clk(clk) , .Q0(q2internal));
|
||||
D_Touch dt3(.D0(t3) , .clk(clk) , .Q0(q3internal));
|
||||
|
||||
assign q1 = q1internal;
|
||||
assign q2 = q2internal;
|
||||
assign q3 = q3internal;
|
||||
|
||||
endmodule
|
||||
|
||||
module test;
|
||||
|
||||
reg clk , a;
|
||||
wire q1 , q2 , q3;
|
||||
|
||||
Light_Time uut (
|
||||
.clk(clk),
|
||||
.a(a),
|
||||
.q1(q1),
|
||||
.q2(q2),
|
||||
.q3(q3)
|
||||
);
|
||||
|
||||
always #2 clk = ~clk;
|
||||
|
||||
initial begin
|
||||
clk = 0;
|
||||
a = 0;
|
||||
$dumpfile("Light_wave.vcd");
|
||||
$dumpvars(0, test);
|
||||
|
||||
// 开始测试
|
||||
#10 a = 1;
|
||||
#100 a = 0;
|
||||
#120 $finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
462
Logisim/Project_Car_Light/Light_wave.vcd
Normal file
462
Logisim/Project_Car_Light/Light_wave.vcd
Normal file
@@ -0,0 +1,462 @@
|
||||
$date
|
||||
Thu May 29 10:38:34 2025
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1ns
|
||||
$end
|
||||
$scope module test $end
|
||||
$var wire 1 ! q3 $end
|
||||
$var wire 1 " q2 $end
|
||||
$var wire 1 # q1 $end
|
||||
$var reg 1 $ a $end
|
||||
$var reg 1 % clk $end
|
||||
$scope module uut $end
|
||||
$var wire 1 $ a $end
|
||||
$var wire 1 % clk $end
|
||||
$var wire 1 # q1 $end
|
||||
$var wire 1 " q2 $end
|
||||
$var wire 1 ! q3 $end
|
||||
$var wire 1 & t1 $end
|
||||
$var wire 1 ' t2 $end
|
||||
$var wire 1 ( t3 $end
|
||||
$var wire 1 ) q3internal $end
|
||||
$var wire 1 * q2internal $end
|
||||
$var wire 1 + q1internal $end
|
||||
$scope module dt1 $end
|
||||
$var wire 1 & D0 $end
|
||||
$var wire 1 % clk $end
|
||||
$var reg 1 + Q0 $end
|
||||
$upscope $end
|
||||
$scope module dt2 $end
|
||||
$var wire 1 ' D0 $end
|
||||
$var wire 1 % clk $end
|
||||
$var reg 1 * Q0 $end
|
||||
$upscope $end
|
||||
$scope module dt3 $end
|
||||
$var wire 1 ( D0 $end
|
||||
$var wire 1 % clk $end
|
||||
$var reg 1 ) Q0 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
$comment Show the parameter values. $end
|
||||
$dumpall
|
||||
$end
|
||||
#0
|
||||
$dumpvars
|
||||
x+
|
||||
x*
|
||||
x)
|
||||
0(
|
||||
0'
|
||||
0&
|
||||
0%
|
||||
0$
|
||||
x#
|
||||
x"
|
||||
x!
|
||||
$end
|
||||
#20
|
||||
0#
|
||||
0+
|
||||
0"
|
||||
0*
|
||||
0!
|
||||
0)
|
||||
1%
|
||||
#40
|
||||
0%
|
||||
#60
|
||||
1%
|
||||
#80
|
||||
0%
|
||||
#100
|
||||
1&
|
||||
1'
|
||||
1(
|
||||
1%
|
||||
1$
|
||||
#120
|
||||
0%
|
||||
#140
|
||||
0(
|
||||
1!
|
||||
1)
|
||||
1"
|
||||
1*
|
||||
1#
|
||||
1+
|
||||
1%
|
||||
#160
|
||||
0%
|
||||
#180
|
||||
1(
|
||||
0'
|
||||
0!
|
||||
0)
|
||||
1%
|
||||
#200
|
||||
0%
|
||||
#220
|
||||
0(
|
||||
0&
|
||||
1!
|
||||
1)
|
||||
0"
|
||||
0*
|
||||
1%
|
||||
#240
|
||||
0%
|
||||
#260
|
||||
1(
|
||||
1'
|
||||
1&
|
||||
0#
|
||||
0+
|
||||
0!
|
||||
0)
|
||||
1%
|
||||
#280
|
||||
0%
|
||||
#300
|
||||
0(
|
||||
1!
|
||||
1)
|
||||
1"
|
||||
1*
|
||||
1#
|
||||
1+
|
||||
1%
|
||||
#320
|
||||
0%
|
||||
#340
|
||||
1(
|
||||
0'
|
||||
0!
|
||||
0)
|
||||
1%
|
||||
#360
|
||||
0%
|
||||
#380
|
||||
0(
|
||||
0&
|
||||
1!
|
||||
1)
|
||||
0"
|
||||
0*
|
||||
1%
|
||||
#400
|
||||
0%
|
||||
#420
|
||||
1(
|
||||
1'
|
||||
1&
|
||||
0#
|
||||
0+
|
||||
0!
|
||||
0)
|
||||
1%
|
||||
#440
|
||||
0%
|
||||
#460
|
||||
0(
|
||||
1!
|
||||
1)
|
||||
1"
|
||||
1*
|
||||
1#
|
||||
1+
|
||||
1%
|
||||
#480
|
||||
0%
|
||||
#500
|
||||
1(
|
||||
0'
|
||||
0!
|
||||
0)
|
||||
1%
|
||||
#520
|
||||
0%
|
||||
#540
|
||||
0(
|
||||
0&
|
||||
1!
|
||||
1)
|
||||
0"
|
||||
0*
|
||||
1%
|
||||
#560
|
||||
0%
|
||||
#580
|
||||
1(
|
||||
1'
|
||||
1&
|
||||
0#
|
||||
0+
|
||||
0!
|
||||
0)
|
||||
1%
|
||||
#600
|
||||
0%
|
||||
#620
|
||||
0(
|
||||
1!
|
||||
1)
|
||||
1"
|
||||
1*
|
||||
1#
|
||||
1+
|
||||
1%
|
||||
#640
|
||||
0%
|
||||
#660
|
||||
1(
|
||||
0'
|
||||
0!
|
||||
0)
|
||||
1%
|
||||
#680
|
||||
0%
|
||||
#700
|
||||
0(
|
||||
0&
|
||||
1!
|
||||
1)
|
||||
0"
|
||||
0*
|
||||
1%
|
||||
#720
|
||||
0%
|
||||
#740
|
||||
1(
|
||||
1'
|
||||
1&
|
||||
0#
|
||||
0+
|
||||
0!
|
||||
0)
|
||||
1%
|
||||
#760
|
||||
0%
|
||||
#780
|
||||
0(
|
||||
1!
|
||||
1)
|
||||
1"
|
||||
1*
|
||||
1#
|
||||
1+
|
||||
1%
|
||||
#800
|
||||
0%
|
||||
#820
|
||||
1(
|
||||
0'
|
||||
0!
|
||||
0)
|
||||
1%
|
||||
#840
|
||||
0%
|
||||
#860
|
||||
0(
|
||||
0&
|
||||
1!
|
||||
1)
|
||||
0"
|
||||
0*
|
||||
1%
|
||||
#880
|
||||
0%
|
||||
#900
|
||||
1(
|
||||
1'
|
||||
1&
|
||||
0#
|
||||
0+
|
||||
0!
|
||||
0)
|
||||
1%
|
||||
#920
|
||||
0%
|
||||
#940
|
||||
0(
|
||||
1!
|
||||
1)
|
||||
1"
|
||||
1*
|
||||
1#
|
||||
1+
|
||||
1%
|
||||
#960
|
||||
0%
|
||||
#980
|
||||
1(
|
||||
0'
|
||||
0!
|
||||
0)
|
||||
1%
|
||||
#1000
|
||||
0%
|
||||
#1020
|
||||
0(
|
||||
0&
|
||||
1!
|
||||
1)
|
||||
0"
|
||||
0*
|
||||
1%
|
||||
#1040
|
||||
0%
|
||||
#1060
|
||||
1(
|
||||
1'
|
||||
1&
|
||||
0#
|
||||
0+
|
||||
0!
|
||||
0)
|
||||
1%
|
||||
#1080
|
||||
0%
|
||||
#1100
|
||||
1!
|
||||
1)
|
||||
1"
|
||||
1*
|
||||
1#
|
||||
1+
|
||||
0&
|
||||
0'
|
||||
0(
|
||||
1%
|
||||
0$
|
||||
#1120
|
||||
0%
|
||||
#1140
|
||||
0#
|
||||
0+
|
||||
0"
|
||||
0*
|
||||
0!
|
||||
0)
|
||||
1%
|
||||
#1160
|
||||
0%
|
||||
#1180
|
||||
1%
|
||||
#1200
|
||||
0%
|
||||
#1220
|
||||
1%
|
||||
#1240
|
||||
0%
|
||||
#1260
|
||||
1%
|
||||
#1280
|
||||
0%
|
||||
#1300
|
||||
1%
|
||||
#1320
|
||||
0%
|
||||
#1340
|
||||
1%
|
||||
#1360
|
||||
0%
|
||||
#1380
|
||||
1%
|
||||
#1400
|
||||
0%
|
||||
#1420
|
||||
1%
|
||||
#1440
|
||||
0%
|
||||
#1460
|
||||
1%
|
||||
#1480
|
||||
0%
|
||||
#1500
|
||||
1%
|
||||
#1520
|
||||
0%
|
||||
#1540
|
||||
1%
|
||||
#1560
|
||||
0%
|
||||
#1580
|
||||
1%
|
||||
#1600
|
||||
0%
|
||||
#1620
|
||||
1%
|
||||
#1640
|
||||
0%
|
||||
#1660
|
||||
1%
|
||||
#1680
|
||||
0%
|
||||
#1700
|
||||
1%
|
||||
#1720
|
||||
0%
|
||||
#1740
|
||||
1%
|
||||
#1760
|
||||
0%
|
||||
#1780
|
||||
1%
|
||||
#1800
|
||||
0%
|
||||
#1820
|
||||
1%
|
||||
#1840
|
||||
0%
|
||||
#1860
|
||||
1%
|
||||
#1880
|
||||
0%
|
||||
#1900
|
||||
1%
|
||||
#1920
|
||||
0%
|
||||
#1940
|
||||
1%
|
||||
#1960
|
||||
0%
|
||||
#1980
|
||||
1%
|
||||
#2000
|
||||
0%
|
||||
#2020
|
||||
1%
|
||||
#2040
|
||||
0%
|
||||
#2060
|
||||
1%
|
||||
#2080
|
||||
0%
|
||||
#2100
|
||||
1%
|
||||
#2120
|
||||
0%
|
||||
#2140
|
||||
1%
|
||||
#2160
|
||||
0%
|
||||
#2180
|
||||
1%
|
||||
#2200
|
||||
0%
|
||||
#2220
|
||||
1%
|
||||
#2240
|
||||
0%
|
||||
#2260
|
||||
1%
|
||||
#2280
|
||||
0%
|
||||
#2300
|
||||
1%
|
||||
171
Logisim/Project_Car_Light/carlight.needvvp
Normal file
171
Logisim/Project_Car_Light/carlight.needvvp
Normal file
@@ -0,0 +1,171 @@
|
||||
#! /c/Source/iverilog-install/bin/vvp
|
||||
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision - 9;
|
||||
:vpi_module "D:\iverilog\lib\ivl\system.vpi";
|
||||
:vpi_module "D:\iverilog\lib\ivl\vhdl_sys.vpi";
|
||||
:vpi_module "D:\iverilog\lib\ivl\vhdl_textio.vpi";
|
||||
:vpi_module "D:\iverilog\lib\ivl\v2005_math.vpi";
|
||||
:vpi_module "D:\iverilog\lib\ivl\va_math.vpi";
|
||||
S_000001dbb749eac0 .scope module, "test" "test" 2 35;
|
||||
.timescale -8 -9;
|
||||
v000001dbb753d630_0 .var "a", 0 0;
|
||||
v000001dbb753cb90_0 .var "clk", 0 0;
|
||||
v000001dbb753ce10_0 .net "q1", 0 0, L_000001dbb753e640; 1 drivers
|
||||
v000001dbb753c2d0_0 .net "q2", 0 0, L_000001dbb753e790; 1 drivers
|
||||
v000001dbb753c7d0_0 .net "q3", 0 0, L_000001dbb753e720; 1 drivers
|
||||
S_000001dbb749ec50 .scope module, "uut" "Light_Time" 2 40, 2 13 0, S_000001dbb749eac0;
|
||||
.timescale -8 -9;
|
||||
.port_info 0 /INPUT 1 "clk";
|
||||
.port_info 1 /INPUT 1 "a";
|
||||
.port_info 2 /OUTPUT 1 "q1";
|
||||
.port_info 3 /OUTPUT 1 "q2";
|
||||
.port_info 4 /OUTPUT 1 "q3";
|
||||
L_000001dbb74da0e0 .functor AND 1, L_000001dbb753d090, L_000001dbb753d9f0, C4<1>, C4<1>;
|
||||
L_000001dbb74d9f20 .functor AND 1, L_000001dbb74da0e0, L_000001dbb753d4f0, C4<1>, C4<1>;
|
||||
L_000001dbb74d99e0 .functor AND 1, L_000001dbb74d9f20, v000001dbb753d630_0, C4<1>, C4<1>;
|
||||
L_000001dbb74d9ba0 .functor AND 1, v000001dbb74dd900_0, v000001dbb74dde00_0, C4<1>, C4<1>;
|
||||
L_000001dbb753e3a0 .functor AND 1, L_000001dbb74d9ba0, v000001dbb753d630_0, C4<1>, C4<1>;
|
||||
L_000001dbb753eb10 .functor OR 1, L_000001dbb74d99e0, L_000001dbb753e3a0, C4<0>, C4<0>;
|
||||
L_000001dbb753e410 .functor AND 1, L_000001dbb753c550, L_000001dbb753c5f0, C4<1>, C4<1>;
|
||||
L_000001dbb753e170 .functor AND 1, L_000001dbb753e410, L_000001dbb753c230, C4<1>, C4<1>;
|
||||
L_000001dbb753ee20 .functor AND 1, L_000001dbb753e170, v000001dbb753d630_0, C4<1>, C4<1>;
|
||||
L_000001dbb753e9c0 .functor AND 1, v000001dbb74dd900_0, v000001dbb74dde00_0, C4<1>, C4<1>;
|
||||
L_000001dbb753edb0 .functor AND 1, L_000001dbb753e9c0, v000001dbb74dd9a0_0, C4<1>, C4<1>;
|
||||
L_000001dbb753ecd0 .functor AND 1, L_000001dbb753edb0, v000001dbb753d630_0, C4<1>, C4<1>;
|
||||
L_000001dbb753e800 .functor OR 1, L_000001dbb753ee20, L_000001dbb753ecd0, C4<0>, C4<0>;
|
||||
L_000001dbb753e4f0 .functor AND 1, L_000001dbb753c690, L_000001dbb753cc30, C4<1>, C4<1>;
|
||||
L_000001dbb753efe0 .functor AND 1, L_000001dbb753e4f0, L_000001dbb753c730, C4<1>, C4<1>;
|
||||
L_000001dbb753e5d0 .functor AND 1, L_000001dbb753efe0, v000001dbb753d630_0, C4<1>, C4<1>;
|
||||
L_000001dbb753ed40 .functor AND 1, v000001dbb74dd900_0, v000001dbb74dde00_0, C4<1>, C4<1>;
|
||||
L_000001dbb753ef00 .functor AND 1, L_000001dbb753ed40, L_000001dbb753c870, C4<1>, C4<1>;
|
||||
L_000001dbb753ee90 .functor AND 1, L_000001dbb753ef00, v000001dbb753d630_0, C4<1>, C4<1>;
|
||||
L_000001dbb753e560 .functor OR 1, L_000001dbb753e5d0, L_000001dbb753ee90, C4<0>, C4<0>;
|
||||
L_000001dbb753e640 .functor BUFZ 1, v000001dbb74dd900_0, C4<0>, C4<0>, C4<0>;
|
||||
L_000001dbb753e790 .functor BUFZ 1, v000001dbb74dde00_0, C4<0>, C4<0>, C4<0>;
|
||||
L_000001dbb753e720 .functor BUFZ 1, v000001dbb74dd9a0_0, C4<0>, C4<0>, C4<0>;
|
||||
v000001dbb74ddae0_0 .net *"_ivl_1", 0 0, L_000001dbb753d090; 1 drivers
|
||||
v000001dbb74ddb80_0 .net *"_ivl_11", 0 0, L_000001dbb74d99e0; 1 drivers
|
||||
v000001dbb74de620_0 .net *"_ivl_13", 0 0, L_000001dbb74d9ba0; 1 drivers
|
||||
v000001dbb74ddc20_0 .net *"_ivl_15", 0 0, L_000001dbb753e3a0; 1 drivers
|
||||
v000001dbb74dd720_0 .net *"_ivl_19", 0 0, L_000001dbb753c550; 1 drivers
|
||||
v000001dbb74ddcc0_0 .net *"_ivl_21", 0 0, L_000001dbb753c5f0; 1 drivers
|
||||
v000001dbb74ddd60_0 .net *"_ivl_23", 0 0, L_000001dbb753e410; 1 drivers
|
||||
v000001dbb74dd7c0_0 .net *"_ivl_25", 0 0, L_000001dbb753c230; 1 drivers
|
||||
v000001dbb74dd860_0 .net *"_ivl_27", 0 0, L_000001dbb753e170; 1 drivers
|
||||
v000001dbb74de260_0 .net *"_ivl_29", 0 0, L_000001dbb753ee20; 1 drivers
|
||||
v000001dbb74de300_0 .net *"_ivl_3", 0 0, L_000001dbb753d9f0; 1 drivers
|
||||
v000001dbb74de3a0_0 .net *"_ivl_31", 0 0, L_000001dbb753e9c0; 1 drivers
|
||||
v000001dbb753dbd0_0 .net *"_ivl_33", 0 0, L_000001dbb753edb0; 1 drivers
|
||||
v000001dbb753d310_0 .net *"_ivl_35", 0 0, L_000001dbb753ecd0; 1 drivers
|
||||
v000001dbb753df90_0 .net *"_ivl_39", 0 0, L_000001dbb753c690; 1 drivers
|
||||
v000001dbb753da90_0 .net *"_ivl_41", 0 0, L_000001dbb753cc30; 1 drivers
|
||||
v000001dbb753c910_0 .net *"_ivl_43", 0 0, L_000001dbb753e4f0; 1 drivers
|
||||
v000001dbb753c9b0_0 .net *"_ivl_45", 0 0, L_000001dbb753c730; 1 drivers
|
||||
v000001dbb753ca50_0 .net *"_ivl_47", 0 0, L_000001dbb753efe0; 1 drivers
|
||||
v000001dbb753c410_0 .net *"_ivl_49", 0 0, L_000001dbb753e5d0; 1 drivers
|
||||
v000001dbb753cd70_0 .net *"_ivl_5", 0 0, L_000001dbb74da0e0; 1 drivers
|
||||
v000001dbb753caf0_0 .net *"_ivl_51", 0 0, L_000001dbb753ed40; 1 drivers
|
||||
v000001dbb753dd10_0 .net *"_ivl_53", 0 0, L_000001dbb753c870; 1 drivers
|
||||
v000001dbb753ccd0_0 .net *"_ivl_55", 0 0, L_000001dbb753ef00; 1 drivers
|
||||
v000001dbb753ddb0_0 .net *"_ivl_57", 0 0, L_000001dbb753ee90; 1 drivers
|
||||
v000001dbb753c0f0_0 .net *"_ivl_7", 0 0, L_000001dbb753d4f0; 1 drivers
|
||||
v000001dbb753de50_0 .net *"_ivl_9", 0 0, L_000001dbb74d9f20; 1 drivers
|
||||
v000001dbb753c190_0 .net "a", 0 0, v000001dbb753d630_0; 1 drivers
|
||||
v000001dbb753def0_0 .net "clk", 0 0, v000001dbb753cb90_0; 1 drivers
|
||||
v000001dbb753cff0_0 .net "q1", 0 0, L_000001dbb753e640; alias, 1 drivers
|
||||
v000001dbb753db30_0 .net "q1internal", 0 0, v000001dbb74dd900_0; 1 drivers
|
||||
v000001dbb753d130_0 .net "q2", 0 0, L_000001dbb753e790; alias, 1 drivers
|
||||
v000001dbb753d450_0 .net "q2internal", 0 0, v000001dbb74dde00_0; 1 drivers
|
||||
v000001dbb753d270_0 .net "q3", 0 0, L_000001dbb753e720; alias, 1 drivers
|
||||
v000001dbb753c4b0_0 .net "q3internal", 0 0, v000001dbb74dd9a0_0; 1 drivers
|
||||
v000001dbb753c370_0 .net "t1", 0 0, L_000001dbb753eb10; 1 drivers
|
||||
v000001dbb753dc70_0 .net "t2", 0 0, L_000001dbb753e800; 1 drivers
|
||||
v000001dbb753d8b0_0 .net "t3", 0 0, L_000001dbb753e560; 1 drivers
|
||||
L_000001dbb753d090 .reduce/nor v000001dbb74dd900_0;
|
||||
L_000001dbb753d9f0 .reduce/nor v000001dbb74dde00_0;
|
||||
L_000001dbb753d4f0 .reduce/nor v000001dbb74dd9a0_0;
|
||||
L_000001dbb753c550 .reduce/nor v000001dbb74dd900_0;
|
||||
L_000001dbb753c5f0 .reduce/nor v000001dbb74dde00_0;
|
||||
L_000001dbb753c230 .reduce/nor v000001dbb74dd9a0_0;
|
||||
L_000001dbb753c690 .reduce/nor v000001dbb74dd900_0;
|
||||
L_000001dbb753cc30 .reduce/nor v000001dbb74dde00_0;
|
||||
L_000001dbb753c730 .reduce/nor v000001dbb74dd9a0_0;
|
||||
L_000001dbb753c870 .reduce/nor v000001dbb74dd9a0_0;
|
||||
S_000001dbb74e54a0 .scope module, "dt1" "D_Touch" 2 25, 2 2 0, S_000001dbb749ec50;
|
||||
.timescale -8 -9;
|
||||
.port_info 0 /INPUT 1 "D0";
|
||||
.port_info 1 /INPUT 1 "clk";
|
||||
.port_info 2 /OUTPUT 1 "Q0";
|
||||
v000001dbb74ddea0_0 .net "D0", 0 0, L_000001dbb753eb10; alias, 1 drivers
|
||||
v000001dbb74dd900_0 .var "Q0", 0 0;
|
||||
v000001dbb74ddfe0_0 .net "clk", 0 0, v000001dbb753cb90_0; alias, 1 drivers
|
||||
E_000001dbb74da630 .event posedge, v000001dbb74ddfe0_0;
|
||||
S_000001dbb74e5630 .scope module, "dt2" "D_Touch" 2 26, 2 2 0, S_000001dbb749ec50;
|
||||
.timescale -8 -9;
|
||||
.port_info 0 /INPUT 1 "D0";
|
||||
.port_info 1 /INPUT 1 "clk";
|
||||
.port_info 2 /OUTPUT 1 "Q0";
|
||||
v000001dbb74de4e0_0 .net "D0", 0 0, L_000001dbb753e800; alias, 1 drivers
|
||||
v000001dbb74dde00_0 .var "Q0", 0 0;
|
||||
v000001dbb74de120_0 .net "clk", 0 0, v000001dbb753cb90_0; alias, 1 drivers
|
||||
S_000001dbb74e4310 .scope module, "dt3" "D_Touch" 2 27, 2 2 0, S_000001dbb749ec50;
|
||||
.timescale -8 -9;
|
||||
.port_info 0 /INPUT 1 "D0";
|
||||
.port_info 1 /INPUT 1 "clk";
|
||||
.port_info 2 /OUTPUT 1 "Q0";
|
||||
v000001dbb74de580_0 .net "D0", 0 0, L_000001dbb753e560; alias, 1 drivers
|
||||
v000001dbb74dd9a0_0 .var "Q0", 0 0;
|
||||
v000001dbb74de1c0_0 .net "clk", 0 0, v000001dbb753cb90_0; alias, 1 drivers
|
||||
.scope S_000001dbb74e54a0;
|
||||
T_0 ;
|
||||
%wait E_000001dbb74da630;
|
||||
%load/vec4 v000001dbb74ddea0_0;
|
||||
%assign/vec4 v000001dbb74dd900_0, 0;
|
||||
%jmp T_0;
|
||||
.thread T_0;
|
||||
.scope S_000001dbb74e5630;
|
||||
T_1 ;
|
||||
%wait E_000001dbb74da630;
|
||||
%load/vec4 v000001dbb74de4e0_0;
|
||||
%assign/vec4 v000001dbb74dde00_0, 0;
|
||||
%jmp T_1;
|
||||
.thread T_1;
|
||||
.scope S_000001dbb74e4310;
|
||||
T_2 ;
|
||||
%wait E_000001dbb74da630;
|
||||
%load/vec4 v000001dbb74de580_0;
|
||||
%assign/vec4 v000001dbb74dd9a0_0, 0;
|
||||
%jmp T_2;
|
||||
.thread T_2;
|
||||
.scope S_000001dbb749eac0;
|
||||
T_3 ;
|
||||
%delay 20, 0;
|
||||
%load/vec4 v000001dbb753cb90_0;
|
||||
%inv;
|
||||
%store/vec4 v000001dbb753cb90_0, 0, 1;
|
||||
%jmp T_3;
|
||||
.thread T_3;
|
||||
.scope S_000001dbb749eac0;
|
||||
T_4 ;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001dbb753cb90_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001dbb753d630_0, 0, 1;
|
||||
%vpi_call 2 53 "$dumpfile", "Light_wave.vcd" {0 0 0};
|
||||
%vpi_call 2 54 "$dumpvars", 32'sb00000000000000000000000000000000, S_000001dbb749eac0 {0 0 0};
|
||||
%delay 100, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001dbb753d630_0, 0, 1;
|
||||
%delay 1000, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001dbb753d630_0, 0, 1;
|
||||
%delay 1200, 0;
|
||||
%vpi_call 2 59 "$finish" {0 0 0};
|
||||
%end;
|
||||
.thread T_4;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 3;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"Car_Light.v";
|
||||
BIN
Logisim/Project_Car_Light/dianlu.png
Normal file
BIN
Logisim/Project_Car_Light/dianlu.png
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 262 KiB |
BIN
Logisim/Project_Car_Light/timu.jpg
Normal file
BIN
Logisim/Project_Car_Light/timu.jpg
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 1.7 MiB |
Reference in New Issue
Block a user