New Hardware Git

Verilog/ez1/ez.needvvp

@@ -0,0 +1,62 @@
+#! /c/Source/iverilog-install/bin/vvp
+:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision - 9;
+:vpi_module "D:\iverilog\lib\ivl\system.vpi";
+:vpi_module "D:\iverilog\lib\ivl\vhdl_sys.vpi";
+:vpi_module "D:\iverilog\lib\ivl\vhdl_textio.vpi";
+:vpi_module "D:\iverilog\lib\ivl\v2005_math.vpi";
+:vpi_module "D:\iverilog\lib\ivl\va_math.vpi";
+S_000001eb42d09c90 .scope module, "test" "test" 2 12;
+ .timescale -8 -9;
+v000001eb42bc5320_0 .var "a", 0 0;
+v000001eb42bc53c0_0 .var "b", 0 0;
+v000001eb42c0e840_0 .net "c", 0 0, L_000001eb42bc5460;  1 drivers
+S_000001eb42bc5050 .scope module, "nnt" "orDoor" 2 15, 2 2 0, S_000001eb42d09c90;
+ .timescale -8 -9;
+    .port_info 0 /INPUT 1 "a";
+    .port_info 1 /INPUT 1 "b";
+    .port_info 2 /OUTPUT 1 "c";
+L_000001eb42bc5460 .functor OR 1, v000001eb42bc5320_0, v000001eb42bc53c0_0, C4<0>, C4<0>;
+v000001eb42b92fd0_0 .net "a", 0 0, v000001eb42bc5320_0;  1 drivers
+v000001eb42bc51e0_0 .net "b", 0 0, v000001eb42bc53c0_0;  1 drivers
+v000001eb42bc5280_0 .net "c", 0 0, L_000001eb42bc5460;  alias, 1 drivers
+    .scope S_000001eb42d09c90;
+T_0 ;
+    %vpi_call 2 22 "$dumpfile", "ez.vcd" {0 0 0};
+    %vpi_call 2 23 "$dumpvars", 32'sb00000000000000000000000000000000, S_000001eb42d09c90 {0 0 0};
+    %delay 100, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001eb42bc5320_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001eb42bc53c0_0, 0, 1;
+    %delay 100, 0;
+    %vpi_call 2 26 "$display", "%d %d %d", v000001eb42bc5320_0, v000001eb42bc53c0_0, v000001eb42c0e840_0 {0 0 0};
+    %delay 100, 0;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001eb42bc5320_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001eb42bc53c0_0, 0, 1;
+    %delay 100, 0;
+    %vpi_call 2 29 "$display", "%d %d %d", v000001eb42bc5320_0, v000001eb42bc53c0_0, v000001eb42c0e840_0 {0 0 0};
+    %delay 100, 0;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001eb42bc5320_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v000001eb42bc53c0_0, 0, 1;
+    %delay 100, 0;
+    %vpi_call 2 32 "$display", "%d %d %d", v000001eb42bc5320_0, v000001eb42bc53c0_0, v000001eb42c0e840_0 {0 0 0};
+    %delay 100, 0;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001eb42bc5320_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v000001eb42bc53c0_0, 0, 1;
+    %delay 100, 0;
+    %vpi_call 2 35 "$display", "%d %d %d", v000001eb42bc5320_0, v000001eb42bc53c0_0, v000001eb42c0e840_0 {0 0 0};
+    %end;
+    .thread T_0;
+# The file index is used to find the file name in the following table.
+:file_names 3;
+    "N/A";
+    "<interactive>";
+    "ez.v";

Verilog/ez1/ez.v

@@ -0,0 +1,38 @@
+`timescale 10ns/1ns
+module orDoor (
+    input a,
+    input b,
+    output c
+);
+
+assign c = a || b;
+    
+endmodule
+
+module test;
+    reg a , b;
+    wire c;
+    orDoor nnt(
+        .a(a),
+        .b(b),
+        .c(c)
+    );
+
+    initial begin
+    $dumpfile("ez.vcd");
+    $dumpvars(0 , test);
+
+    #10 a = 0;b = 0;
+    #10 $display("%d %d %d", a , b , c);
+
+    #10 a = 0;b = 1;
+    #10 $display("%d %d %d", a , b , c);
+#10
+    a = 1;b = 0;
+    #10 $display("%d %d %d", a , b , c);
+#10
+    a = 1;b = 1;
+    #10 $display("%d %d %d", a , b , c);
+    end
+
+endmodule   

Verilog/ez1/ez.vcd

@@ -0,0 +1,42 @@
+$date
+	Thu May 29 14:49:58 2025
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1ns
+$end
+$scope module test $end
+$var wire 1 ! c $end
+$var reg 1 " a $end
+$var reg 1 # b $end
+$scope module nnt $end
+$var wire 1 " a $end
+$var wire 1 # b $end
+$var wire 1 ! c $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+$comment Show the parameter values. $end
+$dumpall
+$end
+#0
+$dumpvars
+x#
+x"
+x!
+$end
+#100
+0!
+0#
+0"
+#300
+1!
+1#
+#500
+0#
+1"
+#700
+1#
+#800