New Hardware Git

2025-12-31 19:35:06 +08:00
commit aca5a8aab8
621 changed files with 254727 additions and 0 deletions
--- a/Verilog/ez1/ez.v
+++ b/Verilog/ez1/ez.v
@@ -0,0 +1,38 @@
+`timescale 10ns/1ns
+module orDoor (
+    input a,
+    input b,
+    output c
+);
+
+assign c = a || b;
+    
+endmodule
+
+module test;
+    reg a , b;
+    wire c;
+    orDoor nnt(
+        .a(a),
+        .b(b),
+        .c(c)
+    );
+
+    initial begin
+    $dumpfile("ez.vcd");
+    $dumpvars(0 , test);
+
+    #10 a = 0;b = 0;
+    #10 $display("%d %d %d", a , b , c);
+
+    #10 a = 0;b = 1;
+    #10 $display("%d %d %d", a , b , c);
+#10
+    a = 1;b = 0;
+    #10 $display("%d %d %d", a , b , c);
+#10
+    a = 1;b = 1;
+    #10 $display("%d %d %d", a , b , c);
+    end
+
+endmodule