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Verilog/test/test0/test0_tb.v

@@ -0,0 +1,29 @@
+//`include "test0.v"
+module test_and_gate;
+    reg a, b;          // 定义输入变量
+    wire y;            // 定义输出变量
+
+    // 实例化与门模块
+    and_gate uut (
+        .a(a),
+        .b(b),
+        .y(y)
+    );
+
+    initial begin
+        // dump VCD
+        $dumpfile("and_gate.vcd");
+        $dumpvars(0, test_and_gate);
+        // 显示标题
+        $display("a b | y");
+        $display("---------");
+
+        // 测试所有输入组合
+        a = 0; b = 0; #1 $display("%b %b | %b", a, b, y);
+        a = 0; b = 1; #1 $display("%b %b | %b", a, b, y);
+        a = 1; b = 0; #1 $display("%b %b | %b", a, b, y);
+        a = 1; b = 1; #1 $display("%b %b | %b", a, b, y);
+
+        $finish;
+    end
+endmodule