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e2hang
127
Logisim/Chatper7_hw1_C1C2/count.v
Normal file
127
Logisim/Chatper7_hw1_C1C2/count.v
Normal file
@@ -0,0 +1,127 @@
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`timescale 10ns/1ns
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module DTouch (
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input clk,
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input rst_n,
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input d,
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output reg q
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);
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always @(posedge clk or negedge rst_n) begin
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if (!rst_n)
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q <= 0; // 初始复位为 0
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else
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q <= d;
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end
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endmodule
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//when c1 = 0
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module mode3(
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input c2,
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input clk,
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input rst_n,
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output q1, q0
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);
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wire d0i, d1i;
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wire q0i, q1i;
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assign d1i = ((!q1i) && (!q0i) && c2) || ((!q1i) && (q0i) && (!c2));
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assign d0i = ((!q1i) && (!q0i) && (!c2)) || ((q1i) && (!q0i) && (c2)) ;
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DTouch dd0(.clk(clk), .rst_n(rst_n), .d(d0i), .q(q0i));
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DTouch dd1(.clk(clk), .rst_n(rst_n), .d(d1i), .q(q1i));
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assign q0 = q0i;
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assign q1 = q1i;
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endmodule
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//when c1 = 1
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module mode4(
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input c2,
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input clk,
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input rst_n,
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output q1, q0
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);
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wire d0i, d1i;
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wire q0i, q1i;
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assign d1i = ((!q1i) && (!q0i)) || ((q1i) && (q0i));
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assign d0i = ((q0i) && (!c2)) || ((!q0i) && (c2));
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DTouch dd0(.clk(clk), .rst_n(rst_n), .d(d0i), .q(q0i));
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DTouch dd1(.clk(clk), .rst_n(rst_n), .d(d1i), .q(q1i));
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assign q0 = q0i;
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assign q1 = q1i;
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endmodule
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module main;
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reg clk = 0;
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reg rst_n = 0;
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reg c1 = 0, c2 = 0;
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wire q1, q0;
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// 时钟生成
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always #2 clk = ~clk;
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// 实例化两个模块，但只选择一个输出
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wire q1_m3, q0_m3;
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wire q1_m4, q0_m4;
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mode3 u_mode3 (
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.c2(c2),
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.clk(clk),
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.rst_n(rst_n),
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.q1(q1_m3),
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.q0(q0_m3)
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);
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mode4 u_mode4 (
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.c2(c2),
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.clk(clk),
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.rst_n(rst_n),
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.q1(q1_m4),
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.q0(q0_m4)
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);
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// 根据 c1 选择哪个模块的输出
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assign q1 = (c1 == 0) ? q1_m3 : q1_m4;
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assign q0 = (c1 == 0) ? q0_m3 : q0_m4;
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// 测试输入控制
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initial begin
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$dumpfile("count_out.vcd");
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$dumpvars(0, main);
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// 添加复位：保持一段时间再释放
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rst_n = 0;
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#4 rst_n = 1;
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// 测试序列
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#4 c1 = 0; c2 = 0;
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#10 c2 = 1;
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#10 c2 = 0;
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#10 c2 = 1;
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#10 c2 = 0;
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#10 c1 = 1; c2 = 0;
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#10 c2 = 1;
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#10 c2 = 0;
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#10 c2 = 1;
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#10 c2 = 0;
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#20 $finish;
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end
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endmodule
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306
Logisim/Chatper7_hw1_C1C2/count_out.needvvp
Normal file
306
Logisim/Chatper7_hw1_C1C2/count_out.needvvp
Normal file
@@ -0,0 +1,306 @@
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#! /c/Source/iverilog-install/bin/vvp
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:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
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:ivl_delay_selection "TYPICAL";
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:vpi_time_precision - 9;
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:vpi_module "D:\iverilog\lib\ivl\system.vpi";
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:vpi_module "D:\iverilog\lib\ivl\vhdl_sys.vpi";
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:vpi_module "D:\iverilog\lib\ivl\vhdl_textio.vpi";
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:vpi_module "D:\iverilog\lib\ivl\v2005_math.vpi";
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:vpi_module "D:\iverilog\lib\ivl\va_math.vpi";
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S_000001a28a2245e0 .scope module, "main" "main" 2 66;
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.timescale -8 -9;
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v000001a28a27af70_0 .net *"_ivl_0", 31 0, L_000001a28a27bcc0; 1 drivers
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v000001a28a27b150_0 .net *"_ivl_10", 31 0, L_000001a28a27c800; 1 drivers
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L_000001a28a27d458 .functor BUFT 1, C4<0000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
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v000001a28a27a2f0_0 .net *"_ivl_13", 30 0, L_000001a28a27d458; 1 drivers
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L_000001a28a27d4a0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
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v000001a28a27b1f0_0 .net/2u *"_ivl_14", 31 0, L_000001a28a27d4a0; 1 drivers
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v000001a28a279530_0 .net *"_ivl_16", 0 0, L_000001a28a27b900; 1 drivers
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L_000001a28a27d3c8 .functor BUFT 1, C4<0000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
|
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v000001a28a279490_0 .net *"_ivl_3", 30 0, L_000001a28a27d3c8; 1 drivers
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L_000001a28a27d410 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
|
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v000001a28a27a390_0 .net/2u *"_ivl_4", 31 0, L_000001a28a27d410; 1 drivers
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v000001a28a27a4d0_0 .net *"_ivl_6", 0 0, L_000001a28a27cb20; 1 drivers
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v000001a28a27b400_0 .var "c1", 0 0;
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v000001a28a27bfe0_0 .var "c2", 0 0;
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v000001a28a27b5e0_0 .var "clk", 0 0;
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v000001a28a27b720_0 .net "q0", 0 0, L_000001a28a27c1c0; 1 drivers
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v000001a28a27c940_0 .net "q0_m3", 0 0, L_000001a28a20ced0; 1 drivers
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v000001a28a27b860_0 .net "q0_m4", 0 0, L_000001a28a20c7d0; 1 drivers
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v000001a28a27c120_0 .net "q1", 0 0, L_000001a28a27cbc0; 1 drivers
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v000001a28a27be00_0 .net "q1_m3", 0 0, L_000001a28a20d170; 1 drivers
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v000001a28a27c440_0 .net "q1_m4", 0 0, L_000001a28a20ce60; 1 drivers
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v000001a28a27b540_0 .var "rst_n", 0 0;
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L_000001a28a27bcc0 .concat [ 1 31 0 0], v000001a28a27b400_0, L_000001a28a27d3c8;
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L_000001a28a27cb20 .cmp/eq 32, L_000001a28a27bcc0, L_000001a28a27d410;
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L_000001a28a27cbc0 .functor MUXZ 1, L_000001a28a20ce60, L_000001a28a20d170, L_000001a28a27cb20, C4<>;
|
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L_000001a28a27c800 .concat [ 1 31 0 0], v000001a28a27b400_0, L_000001a28a27d458;
|
||||
L_000001a28a27b900 .cmp/eq 32, L_000001a28a27c800, L_000001a28a27d4a0;
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L_000001a28a27c1c0 .functor MUXZ 1, L_000001a28a20c7d0, L_000001a28a20ced0, L_000001a28a27b900, C4<>;
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S_000001a28a15e9c0 .scope module, "u_mode3" "mode3" 2 81, 2 20 0, S_000001a28a2245e0;
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.timescale -8 -9;
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.port_info 0 /INPUT 1 "c2";
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.port_info 1 /INPUT 1 "clk";
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.port_info 2 /INPUT 1 "rst_n";
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.port_info 3 /OUTPUT 1 "q1";
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.port_info 4 /OUTPUT 1 "q0";
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L_000001a28a20cfb0 .functor AND 1, L_000001a28a27b680, L_000001a28a27ca80, C4<1>, C4<1>;
|
||||
L_000001a28a20cf40 .functor AND 1, L_000001a28a20cfb0, v000001a28a27bfe0_0, C4<1>, C4<1>;
|
||||
L_000001a28a20d2c0 .functor AND 1, L_000001a28a27c8a0, v000001a28a211910_0, C4<1>, C4<1>;
|
||||
L_000001a28a20d100 .functor AND 1, L_000001a28a20d2c0, L_000001a28a27bf40, C4<1>, C4<1>;
|
||||
L_000001a28a20d020 .functor OR 1, L_000001a28a20cf40, L_000001a28a20d100, C4<0>, C4<0>;
|
||||
L_000001a28a20c840 .functor AND 1, L_000001a28a27c080, L_000001a28a27d0c0, C4<1>, C4<1>;
|
||||
L_000001a28a20cbc0 .functor AND 1, L_000001a28a20c840, L_000001a28a27d160, C4<1>, C4<1>;
|
||||
L_000001a28a20d250 .functor AND 1, v000001a28a211eb0_0, L_000001a28a27b7c0, C4<1>, C4<1>;
|
||||
L_000001a28a20d3a0 .functor AND 1, L_000001a28a20d250, v000001a28a27bfe0_0, C4<1>, C4<1>;
|
||||
L_000001a28a20cd10 .functor OR 1, L_000001a28a20cbc0, L_000001a28a20d3a0, C4<0>, C4<0>;
|
||||
L_000001a28a20ced0 .functor BUFZ 1, v000001a28a211910_0, C4<0>, C4<0>, C4<0>;
|
||||
L_000001a28a20d170 .functor BUFZ 1, v000001a28a211eb0_0, C4<0>, C4<0>, C4<0>;
|
||||
v000001a28a211690_0 .net *"_ivl_1", 0 0, L_000001a28a27b680; 1 drivers
|
||||
v000001a28a211f50_0 .net *"_ivl_11", 0 0, L_000001a28a20d2c0; 1 drivers
|
||||
v000001a28a211ff0_0 .net *"_ivl_13", 0 0, L_000001a28a27bf40; 1 drivers
|
||||
v000001a28a212130_0 .net *"_ivl_15", 0 0, L_000001a28a20d100; 1 drivers
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||||
v000001a28a212270_0 .net *"_ivl_19", 0 0, L_000001a28a27c080; 1 drivers
|
||||
v000001a28a212310_0 .net *"_ivl_21", 0 0, L_000001a28a27d0c0; 1 drivers
|
||||
v000001a28a211410_0 .net *"_ivl_23", 0 0, L_000001a28a20c840; 1 drivers
|
||||
v000001a28a2114b0_0 .net *"_ivl_25", 0 0, L_000001a28a27d160; 1 drivers
|
||||
v000001a28a27a890_0 .net *"_ivl_27", 0 0, L_000001a28a20cbc0; 1 drivers
|
||||
v000001a28a2798f0_0 .net *"_ivl_29", 0 0, L_000001a28a27b7c0; 1 drivers
|
||||
v000001a28a279670_0 .net *"_ivl_3", 0 0, L_000001a28a27ca80; 1 drivers
|
||||
v000001a28a27aa70_0 .net *"_ivl_31", 0 0, L_000001a28a20d250; 1 drivers
|
||||
v000001a28a279f30_0 .net *"_ivl_33", 0 0, L_000001a28a20d3a0; 1 drivers
|
||||
v000001a28a27ab10_0 .net *"_ivl_5", 0 0, L_000001a28a20cfb0; 1 drivers
|
||||
v000001a28a27aed0_0 .net *"_ivl_7", 0 0, L_000001a28a20cf40; 1 drivers
|
||||
v000001a28a27ad90_0 .net *"_ivl_9", 0 0, L_000001a28a27c8a0; 1 drivers
|
||||
v000001a28a279cb0_0 .net "c2", 0 0, v000001a28a27bfe0_0; 1 drivers
|
||||
v000001a28a279b70_0 .net "clk", 0 0, v000001a28a27b5e0_0; 1 drivers
|
||||
v000001a28a27abb0_0 .net "d0i", 0 0, L_000001a28a20cd10; 1 drivers
|
||||
v000001a28a279990_0 .net "d1i", 0 0, L_000001a28a20d020; 1 drivers
|
||||
v000001a28a279710_0 .net "q0", 0 0, L_000001a28a20ced0; alias, 1 drivers
|
||||
v000001a28a2793f0_0 .net "q0i", 0 0, v000001a28a211910_0; 1 drivers
|
||||
v000001a28a27a250_0 .net "q1", 0 0, L_000001a28a20d170; alias, 1 drivers
|
||||
v000001a28a279fd0_0 .net "q1i", 0 0, v000001a28a211eb0_0; 1 drivers
|
||||
v000001a28a279850_0 .net "rst_n", 0 0, v000001a28a27b540_0; 1 drivers
|
||||
L_000001a28a27b680 .reduce/nor v000001a28a211eb0_0;
|
||||
L_000001a28a27ca80 .reduce/nor v000001a28a211910_0;
|
||||
L_000001a28a27c8a0 .reduce/nor v000001a28a211eb0_0;
|
||||
L_000001a28a27bf40 .reduce/nor v000001a28a27bfe0_0;
|
||||
L_000001a28a27c080 .reduce/nor v000001a28a211eb0_0;
|
||||
L_000001a28a27d0c0 .reduce/nor v000001a28a211910_0;
|
||||
L_000001a28a27d160 .reduce/nor v000001a28a27bfe0_0;
|
||||
L_000001a28a27b7c0 .reduce/nor v000001a28a211910_0;
|
||||
S_000001a28a15eb50 .scope module, "dd0" "DTouch" 2 33, 2 3 0, S_000001a28a15e9c0;
|
||||
.timescale -8 -9;
|
||||
.port_info 0 /INPUT 1 "clk";
|
||||
.port_info 1 /INPUT 1 "rst_n";
|
||||
.port_info 2 /INPUT 1 "d";
|
||||
.port_info 3 /OUTPUT 1 "q";
|
||||
v000001a28a211550_0 .net "clk", 0 0, v000001a28a27b5e0_0; alias, 1 drivers
|
||||
v000001a28a211a50_0 .net "d", 0 0, L_000001a28a20cd10; alias, 1 drivers
|
||||
v000001a28a211910_0 .var "q", 0 0;
|
||||
v000001a28a211d70_0 .net "rst_n", 0 0, v000001a28a27b540_0; alias, 1 drivers
|
||||
E_000001a28a210090/0 .event negedge, v000001a28a211d70_0;
|
||||
E_000001a28a210090/1 .event posedge, v000001a28a211550_0;
|
||||
E_000001a28a210090 .event/or E_000001a28a210090/0, E_000001a28a210090/1;
|
||||
S_000001a28a21a010 .scope module, "dd1" "DTouch" 2 34, 2 3 0, S_000001a28a15e9c0;
|
||||
.timescale -8 -9;
|
||||
.port_info 0 /INPUT 1 "clk";
|
||||
.port_info 1 /INPUT 1 "rst_n";
|
||||
.port_info 2 /INPUT 1 "d";
|
||||
.port_info 3 /OUTPUT 1 "q";
|
||||
v000001a28a2121d0_0 .net "clk", 0 0, v000001a28a27b5e0_0; alias, 1 drivers
|
||||
v000001a28a211e10_0 .net "d", 0 0, L_000001a28a20d020; alias, 1 drivers
|
||||
v000001a28a211eb0_0 .var "q", 0 0;
|
||||
v000001a28a2115f0_0 .net "rst_n", 0 0, v000001a28a27b540_0; alias, 1 drivers
|
||||
S_000001a28a21a1a0 .scope module, "u_mode4" "mode4" 2 89, 2 43 0, S_000001a28a2245e0;
|
||||
.timescale -8 -9;
|
||||
.port_info 0 /INPUT 1 "c2";
|
||||
.port_info 1 /INPUT 1 "clk";
|
||||
.port_info 2 /INPUT 1 "rst_n";
|
||||
.port_info 3 /OUTPUT 1 "q1";
|
||||
.port_info 4 /OUTPUT 1 "q0";
|
||||
L_000001a28a20d640 .functor AND 1, L_000001a28a27ce40, L_000001a28a27c9e0, C4<1>, C4<1>;
|
||||
L_000001a28a20d330 .functor AND 1, v000001a28a279ad0_0, v000001a28a27a930_0, C4<1>, C4<1>;
|
||||
L_000001a28a20d4f0 .functor OR 1, L_000001a28a20d640, L_000001a28a20d330, C4<0>, C4<0>;
|
||||
L_000001a28a20cd80 .functor AND 1, v000001a28a27a930_0, L_000001a28a27cc60, C4<1>, C4<1>;
|
||||
L_000001a28a20ca70 .functor AND 1, L_000001a28a27c300, v000001a28a27bfe0_0, C4<1>, C4<1>;
|
||||
L_000001a28a20cb50 .functor OR 1, L_000001a28a20cd80, L_000001a28a20ca70, C4<0>, C4<0>;
|
||||
L_000001a28a20c7d0 .functor BUFZ 1, v000001a28a27a930_0, C4<0>, C4<0>, C4<0>;
|
||||
L_000001a28a20ce60 .functor BUFZ 1, v000001a28a279ad0_0, C4<0>, C4<0>, C4<0>;
|
||||
v000001a28a27a6b0_0 .net *"_ivl_1", 0 0, L_000001a28a27ce40; 1 drivers
|
||||
v000001a28a279c10_0 .net *"_ivl_11", 0 0, L_000001a28a27cc60; 1 drivers
|
||||
v000001a28a27a070_0 .net *"_ivl_13", 0 0, L_000001a28a20cd80; 1 drivers
|
||||
v000001a28a279df0_0 .net *"_ivl_15", 0 0, L_000001a28a27c300; 1 drivers
|
||||
v000001a28a27b290_0 .net *"_ivl_17", 0 0, L_000001a28a20ca70; 1 drivers
|
||||
v000001a28a27b010_0 .net *"_ivl_3", 0 0, L_000001a28a27c9e0; 1 drivers
|
||||
v000001a28a27a570_0 .net *"_ivl_5", 0 0, L_000001a28a20d640; 1 drivers
|
||||
v000001a28a27acf0_0 .net *"_ivl_7", 0 0, L_000001a28a20d330; 1 drivers
|
||||
v000001a28a27ae30_0 .net "c2", 0 0, v000001a28a27bfe0_0; alias, 1 drivers
|
||||
v000001a28a279e90_0 .net "clk", 0 0, v000001a28a27b5e0_0; alias, 1 drivers
|
||||
v000001a28a27a750_0 .net "d0i", 0 0, L_000001a28a20cb50; 1 drivers
|
||||
v000001a28a27a110_0 .net "d1i", 0 0, L_000001a28a20d4f0; 1 drivers
|
||||
v000001a28a27a7f0_0 .net "q0", 0 0, L_000001a28a20c7d0; alias, 1 drivers
|
||||
v000001a28a27a9d0_0 .net "q0i", 0 0, v000001a28a27a930_0; 1 drivers
|
||||
v000001a28a27a1b0_0 .net "q1", 0 0, L_000001a28a20ce60; alias, 1 drivers
|
||||
v000001a28a2795d0_0 .net "q1i", 0 0, v000001a28a279ad0_0; 1 drivers
|
||||
v000001a28a27b0b0_0 .net "rst_n", 0 0, v000001a28a27b540_0; alias, 1 drivers
|
||||
L_000001a28a27ce40 .reduce/nor v000001a28a279ad0_0;
|
||||
L_000001a28a27c9e0 .reduce/nor v000001a28a27a930_0;
|
||||
L_000001a28a27cc60 .reduce/nor v000001a28a27bfe0_0;
|
||||
L_000001a28a27c300 .reduce/nor v000001a28a27a930_0;
|
||||
S_000001a28a214400 .scope module, "dd0" "DTouch" 2 56, 2 3 0, S_000001a28a21a1a0;
|
||||
.timescale -8 -9;
|
||||
.port_info 0 /INPUT 1 "clk";
|
||||
.port_info 1 /INPUT 1 "rst_n";
|
||||
.port_info 2 /INPUT 1 "d";
|
||||
.port_info 3 /OUTPUT 1 "q";
|
||||
v000001a28a27a430_0 .net "clk", 0 0, v000001a28a27b5e0_0; alias, 1 drivers
|
||||
v000001a28a27a610_0 .net "d", 0 0, L_000001a28a20cb50; alias, 1 drivers
|
||||
v000001a28a27a930_0 .var "q", 0 0;
|
||||
v000001a28a279d50_0 .net "rst_n", 0 0, v000001a28a27b540_0; alias, 1 drivers
|
||||
S_000001a28a214590 .scope module, "dd1" "DTouch" 2 57, 2 3 0, S_000001a28a21a1a0;
|
||||
.timescale -8 -9;
|
||||
.port_info 0 /INPUT 1 "clk";
|
||||
.port_info 1 /INPUT 1 "rst_n";
|
||||
.port_info 2 /INPUT 1 "d";
|
||||
.port_info 3 /OUTPUT 1 "q";
|
||||
v000001a28a279a30_0 .net "clk", 0 0, v000001a28a27b5e0_0; alias, 1 drivers
|
||||
v000001a28a27ac50_0 .net "d", 0 0, L_000001a28a20d4f0; alias, 1 drivers
|
||||
v000001a28a279ad0_0 .var "q", 0 0;
|
||||
v000001a28a2797b0_0 .net "rst_n", 0 0, v000001a28a27b540_0; alias, 1 drivers
|
||||
.scope S_000001a28a15eb50;
|
||||
T_0 ;
|
||||
%wait E_000001a28a210090;
|
||||
%load/vec4 v000001a28a211d70_0;
|
||||
%nor/r;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_0.0, 8;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%assign/vec4 v000001a28a211910_0, 0;
|
||||
%jmp T_0.1;
|
||||
T_0.0 ;
|
||||
%load/vec4 v000001a28a211a50_0;
|
||||
%assign/vec4 v000001a28a211910_0, 0;
|
||||
T_0.1 ;
|
||||
%jmp T_0;
|
||||
.thread T_0;
|
||||
.scope S_000001a28a21a010;
|
||||
T_1 ;
|
||||
%wait E_000001a28a210090;
|
||||
%load/vec4 v000001a28a2115f0_0;
|
||||
%nor/r;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_1.0, 8;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%assign/vec4 v000001a28a211eb0_0, 0;
|
||||
%jmp T_1.1;
|
||||
T_1.0 ;
|
||||
%load/vec4 v000001a28a211e10_0;
|
||||
%assign/vec4 v000001a28a211eb0_0, 0;
|
||||
T_1.1 ;
|
||||
%jmp T_1;
|
||||
.thread T_1;
|
||||
.scope S_000001a28a214400;
|
||||
T_2 ;
|
||||
%wait E_000001a28a210090;
|
||||
%load/vec4 v000001a28a279d50_0;
|
||||
%nor/r;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_2.0, 8;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%assign/vec4 v000001a28a27a930_0, 0;
|
||||
%jmp T_2.1;
|
||||
T_2.0 ;
|
||||
%load/vec4 v000001a28a27a610_0;
|
||||
%assign/vec4 v000001a28a27a930_0, 0;
|
||||
T_2.1 ;
|
||||
%jmp T_2;
|
||||
.thread T_2;
|
||||
.scope S_000001a28a214590;
|
||||
T_3 ;
|
||||
%wait E_000001a28a210090;
|
||||
%load/vec4 v000001a28a2797b0_0;
|
||||
%nor/r;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_3.0, 8;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%assign/vec4 v000001a28a279ad0_0, 0;
|
||||
%jmp T_3.1;
|
||||
T_3.0 ;
|
||||
%load/vec4 v000001a28a27ac50_0;
|
||||
%assign/vec4 v000001a28a279ad0_0, 0;
|
||||
T_3.1 ;
|
||||
%jmp T_3;
|
||||
.thread T_3;
|
||||
.scope S_000001a28a2245e0;
|
||||
T_4 ;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001a28a27b5e0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001a28a27b540_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001a28a27b400_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001a28a27bfe0_0, 0, 1;
|
||||
%end;
|
||||
.thread T_4;
|
||||
.scope S_000001a28a2245e0;
|
||||
T_5 ;
|
||||
%delay 20, 0;
|
||||
%load/vec4 v000001a28a27b5e0_0;
|
||||
%inv;
|
||||
%store/vec4 v000001a28a27b5e0_0, 0, 1;
|
||||
%jmp T_5;
|
||||
.thread T_5;
|
||||
.scope S_000001a28a2245e0;
|
||||
T_6 ;
|
||||
%vpi_call 2 103 "$dumpfile", "count_out.vcd" {0 0 0};
|
||||
%vpi_call 2 104 "$dumpvars", 32'sb00000000000000000000000000000000, S_000001a28a2245e0 {0 0 0};
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001a28a27b540_0, 0, 1;
|
||||
%delay 40, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001a28a27b540_0, 0, 1;
|
||||
%delay 40, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001a28a27b400_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001a28a27bfe0_0, 0, 1;
|
||||
%delay 100, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001a28a27bfe0_0, 0, 1;
|
||||
%delay 100, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001a28a27bfe0_0, 0, 1;
|
||||
%delay 100, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001a28a27bfe0_0, 0, 1;
|
||||
%delay 100, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001a28a27bfe0_0, 0, 1;
|
||||
%delay 100, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001a28a27b400_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001a28a27bfe0_0, 0, 1;
|
||||
%delay 100, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001a28a27bfe0_0, 0, 1;
|
||||
%delay 100, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001a28a27bfe0_0, 0, 1;
|
||||
%delay 100, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001a28a27bfe0_0, 0, 1;
|
||||
%delay 100, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001a28a27bfe0_0, 0, 1;
|
||||
%delay 200, 0;
|
||||
%vpi_call 2 123 "$finish" {0 0 0};
|
||||
%end;
|
||||
.thread T_6;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 3;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"count.v";
|
||||
478
Logisim/Chatper7_hw1_C1C2/count_out.vcd
Normal file
478
Logisim/Chatper7_hw1_C1C2/count_out.vcd
Normal file
@@ -0,0 +1,478 @@
|
||||
$date
|
||||
Fri May 30 08:26:55 2025
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1ns
|
||||
$end
|
||||
$scope module main $end
|
||||
$var wire 1 ! q1_m4 $end
|
||||
$var wire 1 " q1_m3 $end
|
||||
$var wire 1 # q1 $end
|
||||
$var wire 1 $ q0_m4 $end
|
||||
$var wire 1 % q0_m3 $end
|
||||
$var wire 1 & q0 $end
|
||||
$var reg 1 ' c1 $end
|
||||
$var reg 1 ( c2 $end
|
||||
$var reg 1 ) clk $end
|
||||
$var reg 1 * rst_n $end
|
||||
$scope module u_mode3 $end
|
||||
$var wire 1 ( c2 $end
|
||||
$var wire 1 ) clk $end
|
||||
$var wire 1 + d0i $end
|
||||
$var wire 1 , d1i $end
|
||||
$var wire 1 % q0 $end
|
||||
$var wire 1 " q1 $end
|
||||
$var wire 1 * rst_n $end
|
||||
$var wire 1 - q1i $end
|
||||
$var wire 1 . q0i $end
|
||||
$scope module dd0 $end
|
||||
$var wire 1 ) clk $end
|
||||
$var wire 1 + d $end
|
||||
$var wire 1 * rst_n $end
|
||||
$var reg 1 . q $end
|
||||
$upscope $end
|
||||
$scope module dd1 $end
|
||||
$var wire 1 ) clk $end
|
||||
$var wire 1 , d $end
|
||||
$var wire 1 * rst_n $end
|
||||
$var reg 1 - q $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module u_mode4 $end
|
||||
$var wire 1 ( c2 $end
|
||||
$var wire 1 ) clk $end
|
||||
$var wire 1 / d0i $end
|
||||
$var wire 1 0 d1i $end
|
||||
$var wire 1 $ q0 $end
|
||||
$var wire 1 ! q1 $end
|
||||
$var wire 1 * rst_n $end
|
||||
$var wire 1 1 q1i $end
|
||||
$var wire 1 2 q0i $end
|
||||
$scope module dd0 $end
|
||||
$var wire 1 ) clk $end
|
||||
$var wire 1 / d $end
|
||||
$var wire 1 * rst_n $end
|
||||
$var reg 1 2 q $end
|
||||
$upscope $end
|
||||
$scope module dd1 $end
|
||||
$var wire 1 ) clk $end
|
||||
$var wire 1 0 d $end
|
||||
$var wire 1 * rst_n $end
|
||||
$var reg 1 1 q $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
$comment Show the parameter values. $end
|
||||
$dumpall
|
||||
$end
|
||||
#0
|
||||
$dumpvars
|
||||
02
|
||||
01
|
||||
10
|
||||
0/
|
||||
0.
|
||||
0-
|
||||
0,
|
||||
1+
|
||||
0*
|
||||
0)
|
||||
0(
|
||||
0'
|
||||
0&
|
||||
0%
|
||||
0$
|
||||
0#
|
||||
0"
|
||||
0!
|
||||
$end
|
||||
#20
|
||||
1)
|
||||
#40
|
||||
0)
|
||||
1*
|
||||
#60
|
||||
0+
|
||||
1,
|
||||
00
|
||||
1&
|
||||
1%
|
||||
1.
|
||||
1!
|
||||
11
|
||||
1)
|
||||
#80
|
||||
0)
|
||||
#100
|
||||
0,
|
||||
10
|
||||
1#
|
||||
0&
|
||||
0!
|
||||
01
|
||||
1"
|
||||
1-
|
||||
0%
|
||||
0.
|
||||
1)
|
||||
#120
|
||||
0)
|
||||
#140
|
||||
1+
|
||||
00
|
||||
0#
|
||||
0"
|
||||
0-
|
||||
1!
|
||||
11
|
||||
1)
|
||||
#160
|
||||
0)
|
||||
#180
|
||||
10
|
||||
1&
|
||||
0!
|
||||
01
|
||||
1%
|
||||
1.
|
||||
0,
|
||||
0+
|
||||
1/
|
||||
1)
|
||||
1(
|
||||
#200
|
||||
0)
|
||||
#220
|
||||
1,
|
||||
0/
|
||||
0&
|
||||
0%
|
||||
0.
|
||||
1$
|
||||
12
|
||||
1!
|
||||
11
|
||||
1)
|
||||
#240
|
||||
0)
|
||||
#260
|
||||
0,
|
||||
1+
|
||||
1/
|
||||
00
|
||||
1#
|
||||
0$
|
||||
02
|
||||
1"
|
||||
1-
|
||||
1)
|
||||
#280
|
||||
0+
|
||||
0/
|
||||
0)
|
||||
0(
|
||||
#300
|
||||
1+
|
||||
10
|
||||
0#
|
||||
0"
|
||||
0-
|
||||
0!
|
||||
01
|
||||
1)
|
||||
#320
|
||||
0)
|
||||
#340
|
||||
0+
|
||||
1,
|
||||
00
|
||||
1&
|
||||
1!
|
||||
11
|
||||
1%
|
||||
1.
|
||||
1)
|
||||
#360
|
||||
0)
|
||||
#380
|
||||
1+
|
||||
10
|
||||
0&
|
||||
1#
|
||||
0%
|
||||
0.
|
||||
1"
|
||||
1-
|
||||
0!
|
||||
01
|
||||
0,
|
||||
1/
|
||||
1)
|
||||
1(
|
||||
#400
|
||||
0)
|
||||
#420
|
||||
0+
|
||||
0/
|
||||
0#
|
||||
1&
|
||||
1!
|
||||
11
|
||||
1$
|
||||
12
|
||||
0"
|
||||
0-
|
||||
1%
|
||||
1.
|
||||
1)
|
||||
#440
|
||||
0)
|
||||
#460
|
||||
1,
|
||||
1/
|
||||
00
|
||||
0&
|
||||
0%
|
||||
0.
|
||||
0$
|
||||
02
|
||||
1)
|
||||
#480
|
||||
0,
|
||||
1+
|
||||
0/
|
||||
0)
|
||||
0(
|
||||
#500
|
||||
0+
|
||||
1,
|
||||
10
|
||||
1&
|
||||
0!
|
||||
01
|
||||
1%
|
||||
1.
|
||||
1)
|
||||
#520
|
||||
0)
|
||||
#540
|
||||
0,
|
||||
00
|
||||
0&
|
||||
1#
|
||||
0%
|
||||
0.
|
||||
1"
|
||||
1-
|
||||
1!
|
||||
11
|
||||
1)
|
||||
#560
|
||||
0)
|
||||
#580
|
||||
1+
|
||||
10
|
||||
0#
|
||||
0!
|
||||
01
|
||||
0"
|
||||
0-
|
||||
1)
|
||||
1'
|
||||
#600
|
||||
0)
|
||||
#620
|
||||
0+
|
||||
1,
|
||||
00
|
||||
1#
|
||||
1%
|
||||
1.
|
||||
1!
|
||||
11
|
||||
1)
|
||||
#640
|
||||
0)
|
||||
#660
|
||||
0,
|
||||
10
|
||||
0#
|
||||
0!
|
||||
01
|
||||
1"
|
||||
1-
|
||||
0%
|
||||
0.
|
||||
1)
|
||||
#680
|
||||
1+
|
||||
1/
|
||||
0)
|
||||
1(
|
||||
#700
|
||||
0+
|
||||
0/
|
||||
1&
|
||||
1#
|
||||
1%
|
||||
1.
|
||||
0"
|
||||
0-
|
||||
1$
|
||||
12
|
||||
1!
|
||||
11
|
||||
1)
|
||||
#720
|
||||
0)
|
||||
#740
|
||||
1,
|
||||
1/
|
||||
00
|
||||
0&
|
||||
0$
|
||||
02
|
||||
0%
|
||||
0.
|
||||
1)
|
||||
#760
|
||||
0)
|
||||
#780
|
||||
1&
|
||||
0#
|
||||
1"
|
||||
1-
|
||||
1$
|
||||
12
|
||||
0!
|
||||
01
|
||||
0,
|
||||
0+
|
||||
1/
|
||||
1)
|
||||
0(
|
||||
#800
|
||||
0)
|
||||
#820
|
||||
1+
|
||||
0"
|
||||
0-
|
||||
1)
|
||||
#840
|
||||
0)
|
||||
#860
|
||||
0+
|
||||
1,
|
||||
1%
|
||||
1.
|
||||
1)
|
||||
#880
|
||||
0,
|
||||
0/
|
||||
0)
|
||||
1(
|
||||
#900
|
||||
1,
|
||||
1/
|
||||
10
|
||||
0&
|
||||
0$
|
||||
02
|
||||
0%
|
||||
0.
|
||||
1)
|
||||
#920
|
||||
0)
|
||||
#940
|
||||
0,
|
||||
1+
|
||||
0/
|
||||
1&
|
||||
1#
|
||||
1"
|
||||
1-
|
||||
1$
|
||||
12
|
||||
1!
|
||||
11
|
||||
1)
|
||||
#960
|
||||
0)
|
||||
#980
|
||||
1,
|
||||
00
|
||||
0&
|
||||
0$
|
||||
02
|
||||
0"
|
||||
0-
|
||||
1%
|
||||
1.
|
||||
0+
|
||||
0/
|
||||
1)
|
||||
0(
|
||||
#1000
|
||||
0)
|
||||
#1020
|
||||
0,
|
||||
10
|
||||
0#
|
||||
0%
|
||||
0.
|
||||
1"
|
||||
1-
|
||||
0!
|
||||
01
|
||||
1)
|
||||
#1040
|
||||
0)
|
||||
#1060
|
||||
1+
|
||||
00
|
||||
1#
|
||||
1!
|
||||
11
|
||||
0"
|
||||
0-
|
||||
1)
|
||||
#1080
|
||||
0)
|
||||
#1100
|
||||
0+
|
||||
1,
|
||||
10
|
||||
0#
|
||||
1%
|
||||
1.
|
||||
0!
|
||||
01
|
||||
1)
|
||||
#1120
|
||||
0)
|
||||
#1140
|
||||
0,
|
||||
00
|
||||
1#
|
||||
1!
|
||||
11
|
||||
1"
|
||||
1-
|
||||
0%
|
||||
0.
|
||||
1)
|
||||
#1160
|
||||
0)
|
||||
#1180
|
||||
1+
|
||||
10
|
||||
0#
|
||||
0"
|
||||
0-
|
||||
0!
|
||||
01
|
||||
1)
|
||||
306
Logisim/Chatper7_hw1_C1C2/needvvp
Normal file
306
Logisim/Chatper7_hw1_C1C2/needvvp
Normal file
@@ -0,0 +1,306 @@
|
||||
#! /c/Source/iverilog-install/bin/vvp
|
||||
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision - 9;
|
||||
:vpi_module "D:\iverilog\lib\ivl\system.vpi";
|
||||
:vpi_module "D:\iverilog\lib\ivl\vhdl_sys.vpi";
|
||||
:vpi_module "D:\iverilog\lib\ivl\vhdl_textio.vpi";
|
||||
:vpi_module "D:\iverilog\lib\ivl\v2005_math.vpi";
|
||||
:vpi_module "D:\iverilog\lib\ivl\va_math.vpi";
|
||||
S_00000202ecc44580 .scope module, "main" "main" 2 66;
|
||||
.timescale -8 -9;
|
||||
v00000202ecc9abf0_0 .net *"_ivl_0", 31 0, L_00000202ecc9c340; 1 drivers
|
||||
v00000202ecc9add0_0 .net *"_ivl_10", 31 0, L_00000202ecc9b8a0; 1 drivers
|
||||
L_00000202ecc9d3f8 .functor BUFT 1, C4<0000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
|
||||
v00000202ecc994d0_0 .net *"_ivl_13", 30 0, L_00000202ecc9d3f8; 1 drivers
|
||||
L_00000202ecc9d440 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
|
||||
v00000202ecc9afb0_0 .net/2u *"_ivl_14", 31 0, L_00000202ecc9d440; 1 drivers
|
||||
v00000202ecc9b0f0_0 .net *"_ivl_16", 0 0, L_00000202ecc9bda0; 1 drivers
|
||||
L_00000202ecc9d368 .functor BUFT 1, C4<0000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
|
||||
v00000202ecc99390_0 .net *"_ivl_3", 30 0, L_00000202ecc9d368; 1 drivers
|
||||
L_00000202ecc9d3b0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
|
||||
v00000202ecc997f0_0 .net/2u *"_ivl_4", 31 0, L_00000202ecc9d3b0; 1 drivers
|
||||
v00000202ecc99430_0 .net *"_ivl_6", 0 0, L_00000202ecc9c700; 1 drivers
|
||||
v00000202ecc9cfc0_0 .var "c1", 0 0;
|
||||
v00000202ecc9c840_0 .var "c2", 0 0;
|
||||
v00000202ecc9ce80_0 .var "clk", 0 0;
|
||||
v00000202ecc9cd40_0 .net "q0", 0 0, L_00000202ecc9b440; 1 drivers
|
||||
v00000202ecc9cca0_0 .net "q0_m3", 0 0, L_00000202ecc2c990; 1 drivers
|
||||
v00000202ecc9cde0_0 .net "q0_m4", 0 0, L_00000202ecc2c840; 1 drivers
|
||||
v00000202ecc9bf80_0 .net "q1", 0 0, L_00000202ecc9ca20; 1 drivers
|
||||
v00000202ecc9d060_0 .net "q1_m3", 0 0, L_00000202ecc2c920; 1 drivers
|
||||
v00000202ecc9c8e0_0 .net "q1_m4", 0 0, L_00000202ecc2d330; 1 drivers
|
||||
v00000202ecc9c7a0_0 .var "rst_n", 0 0;
|
||||
L_00000202ecc9c340 .concat [ 1 31 0 0], v00000202ecc9cfc0_0, L_00000202ecc9d368;
|
||||
L_00000202ecc9c700 .cmp/eq 32, L_00000202ecc9c340, L_00000202ecc9d3b0;
|
||||
L_00000202ecc9ca20 .functor MUXZ 1, L_00000202ecc2d330, L_00000202ecc2c920, L_00000202ecc9c700, C4<>;
|
||||
L_00000202ecc9b8a0 .concat [ 1 31 0 0], v00000202ecc9cfc0_0, L_00000202ecc9d3f8;
|
||||
L_00000202ecc9bda0 .cmp/eq 32, L_00000202ecc9b8a0, L_00000202ecc9d440;
|
||||
L_00000202ecc9b440 .functor MUXZ 1, L_00000202ecc2c840, L_00000202ecc2c990, L_00000202ecc9bda0, C4<>;
|
||||
S_00000202ecd3e910 .scope module, "u_mode3" "mode3" 2 81, 2 20 0, S_00000202ecc44580;
|
||||
.timescale -8 -9;
|
||||
.port_info 0 /INPUT 1 "c2";
|
||||
.port_info 1 /INPUT 1 "clk";
|
||||
.port_info 2 /INPUT 1 "rst_n";
|
||||
.port_info 3 /OUTPUT 1 "q1";
|
||||
.port_info 4 /OUTPUT 1 "q0";
|
||||
L_00000202ecc2d5d0 .functor AND 1, L_00000202ecc9bbc0, L_00000202ecc9d240, C4<1>, C4<1>;
|
||||
L_00000202ecc2d020 .functor AND 1, L_00000202ecc2d5d0, v00000202ecc9c840_0, C4<1>, C4<1>;
|
||||
L_00000202ecc2d100 .functor AND 1, L_00000202ecc9cf20, v00000202ecc31870_0, C4<1>, C4<1>;
|
||||
L_00000202ecc2c7d0 .functor AND 1, L_00000202ecc2d100, L_00000202ecc9bee0, C4<1>, C4<1>;
|
||||
L_00000202ecc2d1e0 .functor OR 1, L_00000202ecc2d020, L_00000202ecc2c7d0, C4<0>, C4<0>;
|
||||
L_00000202ecc2d560 .functor AND 1, L_00000202ecc9bd00, L_00000202ecc9be40, C4<1>, C4<1>;
|
||||
L_00000202ecc2d640 .functor AND 1, L_00000202ecc2d560, L_00000202ecc9c980, C4<1>, C4<1>;
|
||||
L_00000202ecc2cd10 .functor AND 1, v00000202ecc31690_0, L_00000202ecc9d100, C4<1>, C4<1>;
|
||||
L_00000202ecc2cfb0 .functor AND 1, L_00000202ecc2cd10, v00000202ecc9c840_0, C4<1>, C4<1>;
|
||||
L_00000202ecc2ca70 .functor OR 1, L_00000202ecc2d640, L_00000202ecc2cfb0, C4<0>, C4<0>;
|
||||
L_00000202ecc2c990 .functor BUFZ 1, v00000202ecc31870_0, C4<0>, C4<0>, C4<0>;
|
||||
L_00000202ecc2c920 .functor BUFZ 1, v00000202ecc31690_0, C4<0>, C4<0>, C4<0>;
|
||||
v00000202ecc317d0_0 .net *"_ivl_1", 0 0, L_00000202ecc9bbc0; 1 drivers
|
||||
v00000202ecc31c30_0 .net *"_ivl_11", 0 0, L_00000202ecc2d100; 1 drivers
|
||||
v00000202ecc31910_0 .net *"_ivl_13", 0 0, L_00000202ecc9bee0; 1 drivers
|
||||
v00000202ecc31d70_0 .net *"_ivl_15", 0 0, L_00000202ecc2c7d0; 1 drivers
|
||||
v00000202ecc319b0_0 .net *"_ivl_19", 0 0, L_00000202ecc9bd00; 1 drivers
|
||||
v00000202ecc31e10_0 .net *"_ivl_21", 0 0, L_00000202ecc9be40; 1 drivers
|
||||
v00000202ecc31f50_0 .net *"_ivl_23", 0 0, L_00000202ecc2d560; 1 drivers
|
||||
v00000202ecc32130_0 .net *"_ivl_25", 0 0, L_00000202ecc9c980; 1 drivers
|
||||
v00000202ecc99890_0 .net *"_ivl_27", 0 0, L_00000202ecc2d640; 1 drivers
|
||||
v00000202ecc99570_0 .net *"_ivl_29", 0 0, L_00000202ecc9d100; 1 drivers
|
||||
v00000202ecc99930_0 .net *"_ivl_3", 0 0, L_00000202ecc9d240; 1 drivers
|
||||
v00000202ecc9ae70_0 .net *"_ivl_31", 0 0, L_00000202ecc2cd10; 1 drivers
|
||||
v00000202ecc9a330_0 .net *"_ivl_33", 0 0, L_00000202ecc2cfb0; 1 drivers
|
||||
v00000202ecc9aa10_0 .net *"_ivl_5", 0 0, L_00000202ecc2d5d0; 1 drivers
|
||||
v00000202ecc9a790_0 .net *"_ivl_7", 0 0, L_00000202ecc2d020; 1 drivers
|
||||
v00000202ecc9a830_0 .net *"_ivl_9", 0 0, L_00000202ecc9cf20; 1 drivers
|
||||
v00000202ecc9b050_0 .net "c2", 0 0, v00000202ecc9c840_0; 1 drivers
|
||||
v00000202ecc9a1f0_0 .net "clk", 0 0, v00000202ecc9ce80_0; 1 drivers
|
||||
v00000202ecc9a3d0_0 .net "d0i", 0 0, L_00000202ecc2ca70; 1 drivers
|
||||
v00000202ecc9a8d0_0 .net "d1i", 0 0, L_00000202ecc2d1e0; 1 drivers
|
||||
v00000202ecc99e30_0 .net "q0", 0 0, L_00000202ecc2c990; alias, 1 drivers
|
||||
v00000202ecc9aab0_0 .net "q0i", 0 0, v00000202ecc31870_0; 1 drivers
|
||||
v00000202ecc9af10_0 .net "q1", 0 0, L_00000202ecc2c920; alias, 1 drivers
|
||||
v00000202ecc999d0_0 .net "q1i", 0 0, v00000202ecc31690_0; 1 drivers
|
||||
v00000202ecc9a970_0 .net "rst_n", 0 0, v00000202ecc9c7a0_0; 1 drivers
|
||||
L_00000202ecc9bbc0 .reduce/nor v00000202ecc31690_0;
|
||||
L_00000202ecc9d240 .reduce/nor v00000202ecc31870_0;
|
||||
L_00000202ecc9cf20 .reduce/nor v00000202ecc31690_0;
|
||||
L_00000202ecc9bee0 .reduce/nor v00000202ecc9c840_0;
|
||||
L_00000202ecc9bd00 .reduce/nor v00000202ecc31690_0;
|
||||
L_00000202ecc9be40 .reduce/nor v00000202ecc31870_0;
|
||||
L_00000202ecc9c980 .reduce/nor v00000202ecc9c840_0;
|
||||
L_00000202ecc9d100 .reduce/nor v00000202ecc31870_0;
|
||||
S_00000202ecd3eaa0 .scope module, "dd0" "DTouch" 2 33, 2 3 0, S_00000202ecd3e910;
|
||||
.timescale -8 -9;
|
||||
.port_info 0 /INPUT 1 "clk";
|
||||
.port_info 1 /INPUT 1 "rst_n";
|
||||
.port_info 2 /INPUT 1 "d";
|
||||
.port_info 3 /OUTPUT 1 "q";
|
||||
v00000202ecc32310_0 .net "clk", 0 0, v00000202ecc9ce80_0; alias, 1 drivers
|
||||
v00000202ecc314b0_0 .net "d", 0 0, L_00000202ecc2ca70; alias, 1 drivers
|
||||
v00000202ecc31870_0 .var "q", 0 0;
|
||||
v00000202ecc31af0_0 .net "rst_n", 0 0, v00000202ecc9c7a0_0; alias, 1 drivers
|
||||
E_00000202ecc2fe50/0 .event negedge, v00000202ecc31af0_0;
|
||||
E_00000202ecc2fe50/1 .event posedge, v00000202ecc32310_0;
|
||||
E_00000202ecc2fe50 .event/or E_00000202ecc2fe50/0, E_00000202ecc2fe50/1;
|
||||
S_00000202ecc39fb0 .scope module, "dd1" "DTouch" 2 34, 2 3 0, S_00000202ecd3e910;
|
||||
.timescale -8 -9;
|
||||
.port_info 0 /INPUT 1 "clk";
|
||||
.port_info 1 /INPUT 1 "rst_n";
|
||||
.port_info 2 /INPUT 1 "d";
|
||||
.port_info 3 /OUTPUT 1 "q";
|
||||
v00000202ecc315f0_0 .net "clk", 0 0, v00000202ecc9ce80_0; alias, 1 drivers
|
||||
v00000202ecc31b90_0 .net "d", 0 0, L_00000202ecc2d1e0; alias, 1 drivers
|
||||
v00000202ecc31690_0 .var "q", 0 0;
|
||||
v00000202ecc31730_0 .net "rst_n", 0 0, v00000202ecc9c7a0_0; alias, 1 drivers
|
||||
S_00000202ecc3a140 .scope module, "u_mode4" "mode4" 2 89, 2 43 0, S_00000202ecc44580;
|
||||
.timescale -8 -9;
|
||||
.port_info 0 /INPUT 1 "c2";
|
||||
.port_info 1 /INPUT 1 "clk";
|
||||
.port_info 2 /INPUT 1 "rst_n";
|
||||
.port_info 3 /OUTPUT 1 "q1";
|
||||
.port_info 4 /OUTPUT 1 "q0";
|
||||
L_00000202ecc2ce60 .functor AND 1, L_00000202ecc9c3e0, L_00000202ecc9d1a0, C4<1>, C4<1>;
|
||||
L_00000202ecc2cae0 .functor AND 1, v00000202ecc99b10_0, v00000202ecc99a70_0, C4<1>, C4<1>;
|
||||
L_00000202ecc2cdf0 .functor OR 1, L_00000202ecc2ce60, L_00000202ecc2cae0, C4<0>, C4<0>;
|
||||
L_00000202ecc2ced0 .functor AND 1, v00000202ecc99a70_0, L_00000202ecc9b3a0, C4<1>, C4<1>;
|
||||
L_00000202ecc2d250 .functor AND 1, L_00000202ecc9b800, v00000202ecc9c840_0, C4<1>, C4<1>;
|
||||
L_00000202ecc2d2c0 .functor OR 1, L_00000202ecc2ced0, L_00000202ecc2d250, C4<0>, C4<0>;
|
||||
L_00000202ecc2c840 .functor BUFZ 1, v00000202ecc99a70_0, C4<0>, C4<0>, C4<0>;
|
||||
L_00000202ecc2d330 .functor BUFZ 1, v00000202ecc99b10_0, C4<0>, C4<0>, C4<0>;
|
||||
v00000202ecc9ad30_0 .net *"_ivl_1", 0 0, L_00000202ecc9c3e0; 1 drivers
|
||||
v00000202ecc9a290_0 .net *"_ivl_11", 0 0, L_00000202ecc9b3a0; 1 drivers
|
||||
v00000202ecc9b190_0 .net *"_ivl_13", 0 0, L_00000202ecc2ced0; 1 drivers
|
||||
v00000202ecc99750_0 .net *"_ivl_15", 0 0, L_00000202ecc9b800; 1 drivers
|
||||
v00000202ecc99ed0_0 .net *"_ivl_17", 0 0, L_00000202ecc2d250; 1 drivers
|
||||
v00000202ecc9a0b0_0 .net *"_ivl_3", 0 0, L_00000202ecc9d1a0; 1 drivers
|
||||
v00000202ecc99f70_0 .net *"_ivl_5", 0 0, L_00000202ecc2ce60; 1 drivers
|
||||
v00000202ecc99bb0_0 .net *"_ivl_7", 0 0, L_00000202ecc2cae0; 1 drivers
|
||||
v00000202ecc9a470_0 .net "c2", 0 0, v00000202ecc9c840_0; alias, 1 drivers
|
||||
v00000202ecc9b230_0 .net "clk", 0 0, v00000202ecc9ce80_0; alias, 1 drivers
|
||||
v00000202ecc9ab50_0 .net "d0i", 0 0, L_00000202ecc2d2c0; 1 drivers
|
||||
v00000202ecc99c50_0 .net "d1i", 0 0, L_00000202ecc2cdf0; 1 drivers
|
||||
v00000202ecc99cf0_0 .net "q0", 0 0, L_00000202ecc2c840; alias, 1 drivers
|
||||
v00000202ecc9a510_0 .net "q0i", 0 0, v00000202ecc99a70_0; 1 drivers
|
||||
v00000202ecc9a5b0_0 .net "q1", 0 0, L_00000202ecc2d330; alias, 1 drivers
|
||||
v00000202ecc9a650_0 .net "q1i", 0 0, v00000202ecc99b10_0; 1 drivers
|
||||
v00000202ecc9a6f0_0 .net "rst_n", 0 0, v00000202ecc9c7a0_0; alias, 1 drivers
|
||||
L_00000202ecc9c3e0 .reduce/nor v00000202ecc99b10_0;
|
||||
L_00000202ecc9d1a0 .reduce/nor v00000202ecc99a70_0;
|
||||
L_00000202ecc9b3a0 .reduce/nor v00000202ecc9c840_0;
|
||||
L_00000202ecc9b800 .reduce/nor v00000202ecc99a70_0;
|
||||
S_00000202ecc34400 .scope module, "dd0" "DTouch" 2 56, 2 3 0, S_00000202ecc3a140;
|
||||
.timescale -8 -9;
|
||||
.port_info 0 /INPUT 1 "clk";
|
||||
.port_info 1 /INPUT 1 "rst_n";
|
||||
.port_info 2 /INPUT 1 "d";
|
||||
.port_info 3 /OUTPUT 1 "q";
|
||||
v00000202ecc9ac90_0 .net "clk", 0 0, v00000202ecc9ce80_0; alias, 1 drivers
|
||||
v00000202ecc99610_0 .net "d", 0 0, L_00000202ecc2d2c0; alias, 1 drivers
|
||||
v00000202ecc99a70_0 .var "q", 0 0;
|
||||
v00000202ecc9a150_0 .net "rst_n", 0 0, v00000202ecc9c7a0_0; alias, 1 drivers
|
||||
S_00000202ecc34590 .scope module, "dd1" "DTouch" 2 57, 2 3 0, S_00000202ecc3a140;
|
||||
.timescale -8 -9;
|
||||
.port_info 0 /INPUT 1 "clk";
|
||||
.port_info 1 /INPUT 1 "rst_n";
|
||||
.port_info 2 /INPUT 1 "d";
|
||||
.port_info 3 /OUTPUT 1 "q";
|
||||
v00000202ecc9a010_0 .net "clk", 0 0, v00000202ecc9ce80_0; alias, 1 drivers
|
||||
v00000202ecc996b0_0 .net "d", 0 0, L_00000202ecc2cdf0; alias, 1 drivers
|
||||
v00000202ecc99b10_0 .var "q", 0 0;
|
||||
v00000202ecc99d90_0 .net "rst_n", 0 0, v00000202ecc9c7a0_0; alias, 1 drivers
|
||||
.scope S_00000202ecd3eaa0;
|
||||
T_0 ;
|
||||
%wait E_00000202ecc2fe50;
|
||||
%load/vec4 v00000202ecc31af0_0;
|
||||
%nor/r;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_0.0, 8;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%assign/vec4 v00000202ecc31870_0, 0;
|
||||
%jmp T_0.1;
|
||||
T_0.0 ;
|
||||
%load/vec4 v00000202ecc314b0_0;
|
||||
%assign/vec4 v00000202ecc31870_0, 0;
|
||||
T_0.1 ;
|
||||
%jmp T_0;
|
||||
.thread T_0;
|
||||
.scope S_00000202ecc39fb0;
|
||||
T_1 ;
|
||||
%wait E_00000202ecc2fe50;
|
||||
%load/vec4 v00000202ecc31730_0;
|
||||
%nor/r;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_1.0, 8;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%assign/vec4 v00000202ecc31690_0, 0;
|
||||
%jmp T_1.1;
|
||||
T_1.0 ;
|
||||
%load/vec4 v00000202ecc31b90_0;
|
||||
%assign/vec4 v00000202ecc31690_0, 0;
|
||||
T_1.1 ;
|
||||
%jmp T_1;
|
||||
.thread T_1;
|
||||
.scope S_00000202ecc34400;
|
||||
T_2 ;
|
||||
%wait E_00000202ecc2fe50;
|
||||
%load/vec4 v00000202ecc9a150_0;
|
||||
%nor/r;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_2.0, 8;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%assign/vec4 v00000202ecc99a70_0, 0;
|
||||
%jmp T_2.1;
|
||||
T_2.0 ;
|
||||
%load/vec4 v00000202ecc99610_0;
|
||||
%assign/vec4 v00000202ecc99a70_0, 0;
|
||||
T_2.1 ;
|
||||
%jmp T_2;
|
||||
.thread T_2;
|
||||
.scope S_00000202ecc34590;
|
||||
T_3 ;
|
||||
%wait E_00000202ecc2fe50;
|
||||
%load/vec4 v00000202ecc99d90_0;
|
||||
%nor/r;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_3.0, 8;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%assign/vec4 v00000202ecc99b10_0, 0;
|
||||
%jmp T_3.1;
|
||||
T_3.0 ;
|
||||
%load/vec4 v00000202ecc996b0_0;
|
||||
%assign/vec4 v00000202ecc99b10_0, 0;
|
||||
T_3.1 ;
|
||||
%jmp T_3;
|
||||
.thread T_3;
|
||||
.scope S_00000202ecc44580;
|
||||
T_4 ;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v00000202ecc9ce80_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v00000202ecc9c7a0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v00000202ecc9cfc0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v00000202ecc9c840_0, 0, 1;
|
||||
%end;
|
||||
.thread T_4;
|
||||
.scope S_00000202ecc44580;
|
||||
T_5 ;
|
||||
%delay 20, 0;
|
||||
%load/vec4 v00000202ecc9ce80_0;
|
||||
%inv;
|
||||
%store/vec4 v00000202ecc9ce80_0, 0, 1;
|
||||
%jmp T_5;
|
||||
.thread T_5;
|
||||
.scope S_00000202ecc44580;
|
||||
T_6 ;
|
||||
%vpi_call 2 103 "$dumpfile", "count_out.vcd" {0 0 0};
|
||||
%vpi_call 2 104 "$dumpvars", 32'sb00000000000000000000000000000000, S_00000202ecc44580 {0 0 0};
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v00000202ecc9c7a0_0, 0, 1;
|
||||
%delay 40, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v00000202ecc9c7a0_0, 0, 1;
|
||||
%delay 50, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v00000202ecc9cfc0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v00000202ecc9c840_0, 0, 1;
|
||||
%delay 100, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v00000202ecc9c840_0, 0, 1;
|
||||
%delay 100, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v00000202ecc9c840_0, 0, 1;
|
||||
%delay 100, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v00000202ecc9c840_0, 0, 1;
|
||||
%delay 100, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v00000202ecc9c840_0, 0, 1;
|
||||
%delay 100, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v00000202ecc9cfc0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v00000202ecc9c840_0, 0, 1;
|
||||
%delay 100, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v00000202ecc9c840_0, 0, 1;
|
||||
%delay 100, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v00000202ecc9c840_0, 0, 1;
|
||||
%delay 100, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v00000202ecc9c840_0, 0, 1;
|
||||
%delay 100, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v00000202ecc9c840_0, 0, 1;
|
||||
%delay 200, 0;
|
||||
%vpi_call 2 123 "$finish" {0 0 0};
|
||||
%end;
|
||||
.thread T_6;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 3;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"count.v";
|
||||
162
Logisim/Chatper7_hw1_C1C2/test
Normal file
162
Logisim/Chatper7_hw1_C1C2/test
Normal file
@@ -0,0 +1,162 @@
|
||||
#! /c/Source/iverilog-install/bin/vvp
|
||||
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision - 9;
|
||||
:vpi_module "D:\iverilog\lib\ivl\system.vpi";
|
||||
:vpi_module "D:\iverilog\lib\ivl\vhdl_sys.vpi";
|
||||
:vpi_module "D:\iverilog\lib\ivl\vhdl_textio.vpi";
|
||||
:vpi_module "D:\iverilog\lib\ivl\v2005_math.vpi";
|
||||
:vpi_module "D:\iverilog\lib\ivl\va_math.vpi";
|
||||
S_000002b05a22d480 .scope module, "mode3" "mode3" 2 16;
|
||||
.timescale -8 -9;
|
||||
.port_info 0 /INPUT 1 "c2";
|
||||
.port_info 1 /INPUT 1 "clk";
|
||||
.port_info 2 /OUTPUT 1 "q1";
|
||||
.port_info 3 /OUTPUT 1 "q0";
|
||||
L_000002b05a11adc0 .functor AND 1, L_000002b05a17bee0, L_000002b05a17bf80, C4<1>, C4<1>;
|
||||
o000002b05a12b488 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
L_000002b05a11ae30 .functor AND 1, L_000002b05a11adc0, o000002b05a12b488, C4<1>, C4<1>;
|
||||
L_000002b05a11aab0 .functor AND 1, L_000002b05a17ae00, v000002b05a11caa0_0, C4<1>, C4<1>;
|
||||
L_000002b05a11a9d0 .functor AND 1, L_000002b05a11aab0, L_000002b05a17a0e0, C4<1>, C4<1>;
|
||||
L_000002b05a11ab20 .functor OR 1, L_000002b05a11ae30, L_000002b05a11a9d0, C4<0>, C4<0>;
|
||||
L_000002b05a11a960 .functor AND 1, L_000002b05a17a220, L_000002b05a17b1c0, C4<1>, C4<1>;
|
||||
L_000002b05a11ace0 .functor AND 1, L_000002b05a11a960, L_000002b05a17a7c0, C4<1>, C4<1>;
|
||||
L_000002b05a11ad50 .functor AND 1, v000002b05a11cb40_0, v000002b05a11caa0_0, C4<1>, C4<1>;
|
||||
L_000002b05a11aea0 .functor AND 1, L_000002b05a11ad50, o000002b05a12b488, C4<1>, C4<1>;
|
||||
L_000002b05a11af10 .functor OR 1, L_000002b05a11ace0, L_000002b05a11aea0, C4<0>, C4<0>;
|
||||
L_000002b05a17d100 .functor BUFZ 1, v000002b05a11cb40_0, C4<0>, C4<0>, C4<0>;
|
||||
L_000002b05a17d250 .functor BUFZ 1, v000002b05a11caa0_0, C4<0>, C4<0>, C4<0>;
|
||||
v000002b05a11bc40_0 .net *"_ivl_1", 0 0, L_000002b05a17bee0; 1 drivers
|
||||
v000002b05a11bce0_0 .net *"_ivl_11", 0 0, L_000002b05a11aab0; 1 drivers
|
||||
v000002b05a11bec0_0 .net *"_ivl_13", 0 0, L_000002b05a17a0e0; 1 drivers
|
||||
v000002b05a11c140_0 .net *"_ivl_15", 0 0, L_000002b05a11a9d0; 1 drivers
|
||||
v000002b05a11c780_0 .net *"_ivl_19", 0 0, L_000002b05a17a220; 1 drivers
|
||||
v000002b05a11c280_0 .net *"_ivl_21", 0 0, L_000002b05a17b1c0; 1 drivers
|
||||
v000002b05a11bf60_0 .net *"_ivl_23", 0 0, L_000002b05a11a960; 1 drivers
|
||||
v000002b05a11c1e0_0 .net *"_ivl_25", 0 0, L_000002b05a17a7c0; 1 drivers
|
||||
v000002b05a11c000_0 .net *"_ivl_27", 0 0, L_000002b05a11ace0; 1 drivers
|
||||
v000002b05a11c3c0_0 .net *"_ivl_29", 0 0, L_000002b05a11ad50; 1 drivers
|
||||
v000002b05a11c460_0 .net *"_ivl_3", 0 0, L_000002b05a17bf80; 1 drivers
|
||||
v000002b05a11c500_0 .net *"_ivl_31", 0 0, L_000002b05a11aea0; 1 drivers
|
||||
v000002b05a11c5a0_0 .net *"_ivl_5", 0 0, L_000002b05a11adc0; 1 drivers
|
||||
v000002b05a11c640_0 .net *"_ivl_7", 0 0, L_000002b05a11ae30; 1 drivers
|
||||
v000002b05a11c6e0_0 .net *"_ivl_9", 0 0, L_000002b05a17ae00; 1 drivers
|
||||
v000002b05a11c8c0_0 .net "c2", 0 0, o000002b05a12b488; 0 drivers
|
||||
o000002b05a12afa8 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
v000002b05a11c960_0 .net "clk", 0 0, o000002b05a12afa8; 0 drivers
|
||||
v000002b05a17b760_0 .net "d0i", 0 0, L_000002b05a11af10; 1 drivers
|
||||
v000002b05a17bd00_0 .net "d1i", 0 0, L_000002b05a11ab20; 1 drivers
|
||||
v000002b05a17b8a0_0 .net "q0", 0 0, L_000002b05a17d250; 1 drivers
|
||||
v000002b05a17acc0_0 .net "q0i", 0 0, v000002b05a11caa0_0; 1 drivers
|
||||
v000002b05a17a180_0 .net "q1", 0 0, L_000002b05a17d100; 1 drivers
|
||||
v000002b05a17a540_0 .net "q1i", 0 0, v000002b05a11cb40_0; 1 drivers
|
||||
L_000002b05a17bee0 .reduce/nor v000002b05a11cb40_0;
|
||||
L_000002b05a17bf80 .reduce/nor v000002b05a11caa0_0;
|
||||
L_000002b05a17ae00 .reduce/nor v000002b05a11cb40_0;
|
||||
L_000002b05a17a0e0 .reduce/nor o000002b05a12b488;
|
||||
L_000002b05a17a220 .reduce/nor v000002b05a11cb40_0;
|
||||
L_000002b05a17b1c0 .reduce/nor v000002b05a11caa0_0;
|
||||
L_000002b05a17a7c0 .reduce/nor o000002b05a12b488;
|
||||
S_000002b05a1252b0 .scope module, "dd0" "DTouch" 2 28, 2 3 0, S_000002b05a22d480;
|
||||
.timescale -8 -9;
|
||||
.port_info 0 /INPUT 1 "clk";
|
||||
.port_info 1 /INPUT 1 "d";
|
||||
.port_info 2 /OUTPUT 1 "q";
|
||||
v000002b05a11c0a0_0 .net "clk", 0 0, o000002b05a12afa8; alias, 0 drivers
|
||||
v000002b05a11c320_0 .net "d", 0 0, L_000002b05a11af10; alias, 1 drivers
|
||||
v000002b05a11caa0_0 .var "q", 0 0;
|
||||
E_000002b05a11d590 .event posedge, v000002b05a11c0a0_0;
|
||||
S_000002b05a125440 .scope module, "dd1" "DTouch" 2 29, 2 3 0, S_000002b05a22d480;
|
||||
.timescale -8 -9;
|
||||
.port_info 0 /INPUT 1 "clk";
|
||||
.port_info 1 /INPUT 1 "d";
|
||||
.port_info 2 /OUTPUT 1 "q";
|
||||
v000002b05a11be20_0 .net "clk", 0 0, o000002b05a12afa8; alias, 0 drivers
|
||||
v000002b05a11ca00_0 .net "d", 0 0, L_000002b05a11ab20; alias, 1 drivers
|
||||
v000002b05a11cb40_0 .var "q", 0 0;
|
||||
S_000002b05a22d610 .scope module, "mode4" "mode4" 2 37;
|
||||
.timescale -8 -9;
|
||||
.port_info 0 /INPUT 1 "c2";
|
||||
.port_info 1 /INPUT 1 "clk";
|
||||
.port_info 2 /OUTPUT 1 "q1";
|
||||
.port_info 3 /OUTPUT 1 "q0";
|
||||
L_000002b05a17d6b0 .functor AND 1, L_000002b05a17a860, L_000002b05a17a900, C4<1>, C4<1>;
|
||||
L_000002b05a17d3a0 .functor AND 1, v000002b05a17a2c0_0, v000002b05a17b800_0, C4<1>, C4<1>;
|
||||
L_000002b05a17d640 .functor OR 1, L_000002b05a17d6b0, L_000002b05a17d3a0, C4<0>, C4<0>;
|
||||
L_000002b05a17d720 .functor AND 1, v000002b05a17b800_0, L_000002b05a17b260, C4<1>, C4<1>;
|
||||
o000002b05a12b968 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
L_000002b05a17d480 .functor AND 1, L_000002b05a17a9a0, o000002b05a12b968, C4<1>, C4<1>;
|
||||
L_000002b05a17d800 .functor OR 1, L_000002b05a17d720, L_000002b05a17d480, C4<0>, C4<0>;
|
||||
L_000002b05a17d790 .functor BUFZ 1, v000002b05a17a2c0_0, C4<0>, C4<0>, C4<0>;
|
||||
L_000002b05a17d170 .functor BUFZ 1, v000002b05a17b800_0, C4<0>, C4<0>, C4<0>;
|
||||
v000002b05a17a720_0 .net *"_ivl_1", 0 0, L_000002b05a17a860; 1 drivers
|
||||
v000002b05a17b3a0_0 .net *"_ivl_11", 0 0, L_000002b05a17b260; 1 drivers
|
||||
v000002b05a17a360_0 .net *"_ivl_13", 0 0, L_000002b05a17d720; 1 drivers
|
||||
v000002b05a17afe0_0 .net *"_ivl_15", 0 0, L_000002b05a17a9a0; 1 drivers
|
||||
v000002b05a17b120_0 .net *"_ivl_17", 0 0, L_000002b05a17d480; 1 drivers
|
||||
v000002b05a17be40_0 .net *"_ivl_3", 0 0, L_000002b05a17a900; 1 drivers
|
||||
v000002b05a17bb20_0 .net *"_ivl_5", 0 0, L_000002b05a17d6b0; 1 drivers
|
||||
v000002b05a17b580_0 .net *"_ivl_7", 0 0, L_000002b05a17d3a0; 1 drivers
|
||||
v000002b05a17a400_0 .net "c2", 0 0, o000002b05a12b968; 0 drivers
|
||||
o000002b05a12b5d8 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
v000002b05a17bbc0_0 .net "clk", 0 0, o000002b05a12b5d8; 0 drivers
|
||||
v000002b05a17a4a0_0 .net "d0i", 0 0, L_000002b05a17d800; 1 drivers
|
||||
v000002b05a17b080_0 .net "d1i", 0 0, L_000002b05a17d640; 1 drivers
|
||||
v000002b05a17bda0_0 .net "q0", 0 0, L_000002b05a17d170; 1 drivers
|
||||
v000002b05a17b300_0 .net "q0i", 0 0, v000002b05a17b800_0; 1 drivers
|
||||
v000002b05a17a5e0_0 .net "q1", 0 0, L_000002b05a17d790; 1 drivers
|
||||
v000002b05a17b9e0_0 .net "q1i", 0 0, v000002b05a17a2c0_0; 1 drivers
|
||||
L_000002b05a17a860 .reduce/nor v000002b05a17a2c0_0;
|
||||
L_000002b05a17a900 .reduce/nor v000002b05a17b800_0;
|
||||
L_000002b05a17b260 .reduce/nor o000002b05a12b968;
|
||||
L_000002b05a17a9a0 .reduce/nor v000002b05a17b800_0;
|
||||
S_000002b05a123d20 .scope module, "dd0" "DTouch" 2 50, 2 3 0, S_000002b05a22d610;
|
||||
.timescale -8 -9;
|
||||
.port_info 0 /INPUT 1 "clk";
|
||||
.port_info 1 /INPUT 1 "d";
|
||||
.port_info 2 /OUTPUT 1 "q";
|
||||
v000002b05a17ac20_0 .net "clk", 0 0, o000002b05a12b5d8; alias, 0 drivers
|
||||
v000002b05a17a680_0 .net "d", 0 0, L_000002b05a17d800; alias, 1 drivers
|
||||
v000002b05a17b800_0 .var "q", 0 0;
|
||||
E_000002b05a11da50 .event posedge, v000002b05a17ac20_0;
|
||||
S_000002b05a123eb0 .scope module, "dd1" "DTouch" 2 51, 2 3 0, S_000002b05a22d610;
|
||||
.timescale -8 -9;
|
||||
.port_info 0 /INPUT 1 "clk";
|
||||
.port_info 1 /INPUT 1 "d";
|
||||
.port_info 2 /OUTPUT 1 "q";
|
||||
v000002b05a17bc60_0 .net "clk", 0 0, o000002b05a12b5d8; alias, 0 drivers
|
||||
v000002b05a17ba80_0 .net "d", 0 0, L_000002b05a17d640; alias, 1 drivers
|
||||
v000002b05a17a2c0_0 .var "q", 0 0;
|
||||
.scope S_000002b05a1252b0;
|
||||
T_0 ;
|
||||
%wait E_000002b05a11d590;
|
||||
%load/vec4 v000002b05a11c320_0;
|
||||
%assign/vec4 v000002b05a11caa0_0, 0;
|
||||
%jmp T_0;
|
||||
.thread T_0;
|
||||
.scope S_000002b05a125440;
|
||||
T_1 ;
|
||||
%wait E_000002b05a11d590;
|
||||
%load/vec4 v000002b05a11ca00_0;
|
||||
%assign/vec4 v000002b05a11cb40_0, 0;
|
||||
%jmp T_1;
|
||||
.thread T_1;
|
||||
.scope S_000002b05a123d20;
|
||||
T_2 ;
|
||||
%wait E_000002b05a11da50;
|
||||
%load/vec4 v000002b05a17a680_0;
|
||||
%assign/vec4 v000002b05a17b800_0, 0;
|
||||
%jmp T_2;
|
||||
.thread T_2;
|
||||
.scope S_000002b05a123eb0;
|
||||
T_3 ;
|
||||
%wait E_000002b05a11da50;
|
||||
%load/vec4 v000002b05a17ba80_0;
|
||||
%assign/vec4 v000002b05a17a2c0_0, 0;
|
||||
%jmp T_3;
|
||||
.thread T_3;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 3;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"count.v";
|
||||
Reference in New Issue
Block a user