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Verilog/test/test0/and_gate.vcd

@@ -0,0 +1,32 @@
+$date
+	Thu May 29 09:14:21 2025
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module test_and_gate $end
+$var wire 1 ! y $end
+$var reg 1 " a $end
+$var reg 1 # b $end
+$upscope $end
+$enddefinitions $end
+$comment Show the parameter values. $end
+$dumpall
+$end
+#0
+$dumpvars
+0#
+0"
+z!
+$end
+#1
+1#
+#2
+0#
+1"
+#3
+1#
+#4

Verilog/test/test0/test.needwave

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+#! /c/Source/iverilog-install/bin/vvp
+:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "D:\iverilog\lib\ivl\system.vpi";
+:vpi_module "D:\iverilog\lib\ivl\vhdl_sys.vpi";
+:vpi_module "D:\iverilog\lib\ivl\vhdl_textio.vpi";
+:vpi_module "D:\iverilog\lib\ivl\v2005_math.vpi";
+:vpi_module "D:\iverilog\lib\ivl\va_math.vpi";
+S_0000024a70779790 .scope module, "and_gate" "and_gate" 2 10;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "a";
+    .port_info 1 /INPUT 1 "b";
+    .port_info 2 /OUTPUT 1 "y";
+o0000024a707c6f98 .functor BUFZ 1, C4<z>; HiZ drive
+o0000024a707c6fc8 .functor BUFZ 1, C4<z>; HiZ drive
+L_0000024a707c54e0 .functor AND 1, o0000024a707c6f98, o0000024a707c6fc8, C4<1>, C4<1>;
+v0000024a70792fa0_0 .net "a", 0 0, o0000024a707c6f98;  0 drivers
+v0000024a7077bdf0_0 .net "b", 0 0, o0000024a707c6fc8;  0 drivers
+v0000024a7077a1c0_0 .net "y", 0 0, L_0000024a707c54e0;  1 drivers
+S_0000024a7077bc60 .scope module, "test_and_gate" "test_and_gate" 3 2;
+ .timescale 0 0;
+v0000024a7077a260_0 .var "a", 0 0;
+v0000024a70792720_0 .var "b", 0 0;
+o0000024a707c7118 .functor BUFZ 1, C4<z>; HiZ drive
+v0000024a707927c0_0 .net "y", 0 0, o0000024a707c7118;  0 drivers
+    .scope S_0000024a7077bc60;
+T_0 ;
+    %vpi_call 3 15 "$dumpfile", "and_gate.vcd" {0 0 0};
+    %vpi_call 3 16 "$dumpvars", 32'sb00000000000000000000000000000000, S_0000024a7077bc60 {0 0 0};
+    %vpi_call 3 18 "$display", "a b | y" {0 0 0};
+    %vpi_call 3 19 "$display", "---------" {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0000024a7077a260_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0000024a70792720_0, 0, 1;
+    %delay 1, 0;
+    %vpi_call 3 22 "$display", "%b %b | %b", v0000024a7077a260_0, v0000024a70792720_0, v0000024a707927c0_0 {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0000024a7077a260_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0000024a70792720_0, 0, 1;
+    %delay 1, 0;
+    %vpi_call 3 23 "$display", "%b %b | %b", v0000024a7077a260_0, v0000024a70792720_0, v0000024a707927c0_0 {0 0 0};
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0000024a7077a260_0, 0, 1;
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0000024a70792720_0, 0, 1;
+    %delay 1, 0;
+    %vpi_call 3 24 "$display", "%b %b | %b", v0000024a7077a260_0, v0000024a70792720_0, v0000024a707927c0_0 {0 0 0};
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0000024a7077a260_0, 0, 1;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0000024a70792720_0, 0, 1;
+    %delay 1, 0;
+    %vpi_call 3 25 "$display", "%b %b | %b", v0000024a7077a260_0, v0000024a70792720_0, v0000024a707927c0_0 {0 0 0};
+    %vpi_call 3 27 "$finish" {0 0 0};
+    %end;
+    .thread T_0;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "test0.v";
+    "test0_tb.v";

Verilog/test/test0/test0.v

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+/*
+module test0(
+    input a;
+    input b;
+    output c;
+);
+
+endmodule
+*/
+module and_gate (
+    input a,       // 输入a
+    input b,       // 输入b
+    output y       // 输出y = a & b
+);
+    assign y = a & b;  // 与操作
+endmodule

Verilog/test/test0/test0_tb.v

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+//`include "test0.v"
+module test_and_gate;
+    reg a, b;          // 定义输入变量
+    wire y;            // 定义输出变量
+
+    // 实例化与门模块
+    and_gate uut (
+        .a(a),
+        .b(b),
+        .y(y)
+    );
+
+    initial begin
+        // dump VCD
+        $dumpfile("and_gate.vcd");
+        $dumpvars(0, test_and_gate);
+        // 显示标题
+        $display("a b | y");
+        $display("---------");
+
+        // 测试所有输入组合
+        a = 0; b = 0; #1 $display("%b %b | %b", a, b, y);
+        a = 0; b = 1; #1 $display("%b %b | %b", a, b, y);
+        a = 1; b = 0; #1 $display("%b %b | %b", a, b, y);
+        a = 1; b = 1; #1 $display("%b %b | %b", a, b, y);
+
+        $finish;
+    end
+endmodule